公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
1998 | A New Extended Finite State Machine (EFSM) Model for RTL Design Verification | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
1998 | Libra - A Library-Independent Framework for Post-Layout Performance Optimization | R.C.-Y. Huang; Y. Wang; K.-T. Cheng; CHUNG-YANG HUANG | International Symposium on Physical Design | |||
1999 | Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
2001 | Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |