公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2006 | A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit | Rong-Jyi Yang; Kuan-Hua Chao; Sy-Chyuan Hwu; Chuan-Kang Liang; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 55 | 43 | |
2007 | A 2.5GHz all-digital delay-locked loop in 0.13μm CMOS technology | Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | |||
2006 | A 2.5GHz, 30mW, 0.03mm2, all-digital delay-locked loop | Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits Conference (A-SSCC) | 0 | 0 | |
2006 | A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit | Rong-Jyi Yang; Kuan-Hua Chao; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 26 | 19 | |
2004 | A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet | Rong-Jyi Yang; Shang-Ping Chen; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 66 | 37 | |
2007 | A 40~550MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm | Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 138 | 113 | |
2005 | A fully integrated 1.7-3.125 Gbps clock and data recovery circuit using a gated frequency detector | Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEICE Transactions on Electronics | 0 | 0 | |
2005 | A wide-range multiphase delay-locked loop using mixed-mode VCDLs | Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEICE Transactions on Electronics | 6 | 6 | |
2008 | An all-digital fast-locking programmable DLL-based clock generator | Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 29 | 24 | |
2002 | Gigahertz CMOS monolithic frequency synthesizer | Rong-Jyi Yang; Ming-Zhe Liu; Shen-Iuan Liu; SHEN-IUAN LIU | 2002 VLSI/CAD | |||
2009 | Loop latency reduction technique for all-digital clock and data recovery circuits | I-Fong Chen; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits Conference | 7 | 0 | |
2004 | Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection | Hsiang-Hui Chang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 21 | 12 |