公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2008 | 10Gbps inductorless CDRs with digital frequency calibration | Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 12 | 11 | |
2003 | 1V 4.2mW Fully Integrated 2.5Gb/s CMOS Limiting Amplifier using Folded Active Inductors | Chia-Hsin Wu; Jieh-Wei Liao; Chih-Hun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | 2003 VLSI/CAD | |||
2002 | 2.4 GHz offset-cancelling down-conversion mixer | Chih-Chun Tang; Kun-Hsien Li; Shen-Iuan Liu; SHEN-IUAN LIU | Electronics Letters | 5 | 4 | |
2008 | 20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13μm CMOS | Hong-Lin Chu; Chaung-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits Conference (A-SSCC) | 4 | 0 | |
2008 | 3.5mW W-band frequency divider with wide locking range in 90nm CMOS technology | Kun-Hung Tsai; Lan-Chou Cho; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU | International Solid-State Circuits Conference | 50 | 0 | |
2011 | 3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS | I-Ting Lee; Chiao-Hsing Wang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits Conference (A-SSCC) | 9 | 0 | |
2004 | 5.8-/5.2-/2.4-GHz SiGe LC VCO with Wide Tuning Range | Chun-Yi Kuo; Che-Fu Liang; Shen-Iuan Liu; SHEN-IUAN LIU | 2004 VLSI/CAD Symposium | |||
2008 | 93.5~ 109.4GHz CMOS injection-locked frequency divider with 15.3% locking range | Lan-Chou Cho; Kun-Hung Tsai; Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU | 2008 Symposium on VLSI Circuits | 26 | 0 | |
2005 | A 0.1-25.5-GHz differential cascaded-distributed amplifier in 0.18-μm CMOS Technology | Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits | 12 | 0 | |
2006 | A 0.18μm CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems | Yen-Horng Chen; Chih-Wei Wang; Ching-Feng Lee; Jen-Lung Liu; Tzu-Yi Yang; Chih-Fan Liao; Che-Fu Liang; Gin-Kou Ma; Shen-Iuan Liu; SHEN-IUAN LIU | 2006 RFIC Symposium | |||
2006 | A 1 v phase locked loop with leakage compensation in 0.13 μm CMOS technology | Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU | IEICE Transactions on Electronics | 10 | 6 | |
2004 | A 1-V 10.7-MHz fourth-order bandpass Delta Sigma modulators using two switched opamps | Chien-Hung Kuo; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 13 | 10 | |
2010 | A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression | Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU | International Symposium on VLSI Design, Automation & Test | 10 | 0 | |
2006 | A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology | Chihun Lee; Lan-Cho Chou; Shen-Iuan Liu; Chun-Lin Ko; Ying-Zong Juang; Chin-Fong Chiu; SHEN-IUAN LIU | 2006 Symposium on VLSI Circuits | 4 | 0 | |
2007 | A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology | Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 4 | ||
2009 | A 1.5GHz all-digital spread spectrum clock generator | Sheng-You Lin; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 56 | 44 | |
2009 | A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS | Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU | IET Circuits, Devices & Systems | 6 | 3 | |
2004 | A 1.5V 12-bit 16MS/s pipelined CMOS ADC with 68dB dynamic range | Ming-Huang Liu; Wei-Yang Ou; Tsung-Yi Su; Kuo-Chan Huang; Shen-Iuan Liu; SHEN-IUAN LIU | Journal of Analog Integrated Circuits and Signal Processings | 7 | 4 | |
2007 | A 10-bit 100MS/s pipelined ADC in 0.18μm CMOS technology | Hwei-Yu Lee; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE International SOC Conference | 2 | 0 | |
2013 | A 10-Gb/s adaptive parallel receiver with joint XTC and DFE using power detection | Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 12 | 10 |