公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2006 | A 10Gbps burst-mode CDR circuit in 0.18μm CMOS | Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Custom Integrated Circuits Conference | 23 | 0 | |
2006 | A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit | Rong-Jyi Yang; Kuan-Hua Chao; Sy-Chyuan Hwu; Chuan-Kang Liang; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 55 | 43 | |
2005 | A 2.5Gbps burst-mode clock and data recovery circuit | Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits | 2 | 0 | |
2007 | A jitter-tolerance-enhanced CDR using a GDCO-based phase detector | Che-Fu Liang; Sy-Chyuan Hwu; SHEN-IUAN LIU | 2007 Symposium on VLSI Circuits | 0 | 9 | |
2008 | A jitter-tolerance-enhanced CDR using a GDCO-based phase detector | Che-Fu Liang; Sy-Chyuan Hwu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 10 | 9 | |
2007 | A multi-band burst-mode clock and data recovery circuit | Che-Fu Liang; Sy-Chyuan Hwu; SHEN-IUAN LIU | IEICE Transactions on Electronics | 5 | 2 |