公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2017 | A 10-Gb/s Equalizer with Digital Adaptation | J-C Hsiao; T-C Lee; TAI-CHENG LEE | International SoC Design Conference | 0 | 0 | |
2018 | A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration | C-Y Lin; Y-H Wei; T-C Lee; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | 29 | 0 | |
2016 | A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique | C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part I | 24 | 22 | |
0 | A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration | 5. Y-H Wei; C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) | 13 | 0 | |
2014 | 2.4-GHz High-Efficiency Adaptive Power Harvester | C-C Lee; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Very Large Scale Integration Systems | 56 | 49 | |
2016 | A 200-MS/s Phase-Detector-Based Comparator with 400-uVrms Noise | C-Y Lin; C-H Wong; C-H Hsu; Y-H Wei; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part II | |||
2016 | A 2X25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology | B-C Lin; W-S Chang; T-C Lee; TAI-CHENG LEE | IEEE VLSI-DAT | 0 | 0 | |
2016 | A 5 GHz Fractional- N ADC-Based Digital Phase-Locked Loops With ?243.8 dB FOM | W-S Chang; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part I | |||
2018 | A 5-GHz Chirp Frequency Synthesizer with a Low 1/f Noise LC Oscillator | T-C Lee; D-N Jhou; TAI-CHENG LEE | PIERS 2018 | |||
2017 | A 5.12-GHz Fractional-N clock multiplier with an LC-VCO-based MDLL | D-N Jhou; W-S Chang; T-C Lee; TAI-CHENG LEE | IEEE Symposium on VLSI Circuits | |||
2011 | A 10-b 400Ms/s 36mW interleaved ADC | Y-C Huang; C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE RFIT Symposium | |||
2011 | A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques | Y-C Huang; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part I | 20 | 18 | |
2012 | A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter | C-C Ho; T-C Lee; TAI-CHENG LEE | IEEE VLSI DAT | 1 | 0 | |
2014 | A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique | C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE Symposium on VLSI Circuits | 26 | 0 | |
2014 | A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise | P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | |||
2014 | A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise | P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE | International Solid-State Circuit Conference | |||
2014 | A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator | Y-H Kang; C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE ISCAS | |||
2010 | A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay | Y-C Hung; K Fong; T-C Lee; TAI-CHENG LEE | IEEE Asian Solid-State Circuit Conference | 0 | 0 | |
2010 | A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB | K-T Chen; T-C Lee; TAI-CHENG LEE | International Journal of Electrical Engineering | |||
2014 | A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth | J-A Cheng; W-S Chang; T-C Lee; TAI-CHENG LEE | IEEE VLSI-DAT | 1 | 0 |