公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2001 | A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits | Ruan, Shanq-Jang; Shang, Rung-Ji; Lai, Feipei; Tsai, Kun-Lin | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2005 | Bipartitioning and encoding in low-power pipelined circuits | Ruan, Shanq-Jang; Tsai, Kun-Lin; Naroska, Edwin; FEI-PEI LAI | ACM Transactions on Design Automation of Electronic Systems | 4 | 3 | |
2004 | Circuit Partition and Reordering Technique for Low Power IP | Tsai, Kun-Lin; Ruan, Shanq-Jang; Huang, Chun-Ming; Naroska, Edwin; Lai, Feipei | IEICE Trans. On Electronics E87-C | | | |
2000 | An effective output-oriented algorithm for low power multipartition architecture | Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Lai, Feipei; Tsai, Kun-Lin; FEI-PEI LAI | Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on | 6 | 0 | |
2001 | An entropy-based algorithm to reduce area overhead for bipartition-codec architecture | Chen, Po-Hung; Ruan, Shanq-Jang; Wu, Kuen-Pin; Hu, Dai-Xun; Lai, Feipei; Tsai, Kun-Lin | Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on | 2 | 0 | |
2005 | Low Power Dynamic Bus Encoding for Deep Sub-micron Design | Tsai, Kun-Lin; Ruan, Shanq-Jang; Chen, Li-Wei; Lai Feipei; Naroska, Edwin | The 3rd International IEEE Northeast Workshop on Circuits & Systems, June 19-22 | | | |
2005 | A low power scheduling method using dual V/sub dd/ and dual V/sub th/ | Tsai, Kun-Lin; Chang, Szu-Wei; Lai, Feipei; FEI-PEI LAI | Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on | 1 | 0 | |
2006 | Low Power Scheduling Method using Multiple Supply Voltages | Tsai, Kun-Lin; Lee, Ju-Yueh; Ruan, Shanq-Jang; Lai, Feipei | IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24 | | | |
2006 | 使用多重電壓之低功率高階合成方法 | 蔡坤霖; Tsai, Kun-Lin | | | | |
2005 | 量子點紅外線偵測器之成長與光電特性 | 蔡昆霖; Tsai, Kun-Lin | | | | |