Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
---|---|---|---|---|---|---|
2009 | A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input | X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG | International Journal of Electrical Engineering | |||
2013 | A mutual characterization based SAR ADC self-testing technique | H.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
2011 | A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager | X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
2006 | A routability constrained scan chain ordering technique for test power reduction | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 8 | ||
2012 | A SAR ADC missing-decision level detection and removal technique | X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | VLSI Test Symposium | 0 | 0 | |
2011 | A self-testing and calibration method for embedded successive approximation register ADC | X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 11 | 0 | |
2009 | A Self-Testing Assisted Pipelined-ADC Calibration Technique | J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG | International Conference on ASIC | |||
2011 | ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 16 | 14 | |
2013 | An IDDQ-Based Source Driver IC Design-for-Test Technique | S.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 0 | 0 | |
2012 | An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration | X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 5 | 5 | |
2009 | An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing | C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 1 | 0 | |
2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 | |
2009 | Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automatic Conference | |||
2009 | Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC | X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 1 | 0 | |
2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium |