公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2007 | 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. | Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; CHIA-LIN YANG ; CHI-SHENG SHIH ; TEI-WEI KUO ; LIANG-GEE CHEN ; YAO-WEN CHANG ; SHAO-YI CHIEN | Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China | 0 | 0 | |
2009 | A multi-core architecture based parallel framework for h.264/avc deblocking filters | Wang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin; Wu, Ja-Ling; JA-LING WU ; CHIA-LIN YANG | Journal of Signal Processing Systems | 16 | 13 | |
2009 | A predictive shutdown technique for GPU shader processors | CHIA-LIN YANG ; Wang, Po-Han; Chen, Yen-Ming; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG | IEEE Computer Architecture Letters | | | |
2008 | A progressive-ILP based routing algorithm for cross-referencing biochips | Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG | Design Automation Conference | 69 | 0 | |
2012 | Age-based PCM wear leveling with nearly zero search cost. | Chen, Chi-Hao; Hsiu, Pi-Cheng; Kuo, Tei-Wei; Yang, Chia-Lin; TEI-WEI KUO ; CHIA-LIN YANG | The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 | 85 | 0 | |
2006 | Branch behavior characterization for multimedia applications | Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG | Advances in Computer Systems Architecture, Proceedings | | | |
2006 | Branch Behavior Characterization for Multimedia Applications. | Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG | Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings | | | |
2015 | A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. | Lin, Ye-Jyun; Yang, Chia-Lin; Li, Hsiang-Pang; CHIA-LIN YANG | IEEE Non-Volatile Memory System and Applications Symposium, NVMSA 2015, Hong Kong, China, August 19-21, 2015 | 14 | 0 | |
2012 | A cycle-level SIMT-GPU simulation framework. | Wang, Po-Han; Lo, Chien-Wei; Yang, Chia-Lin; CHIA-LIN YANG | 2012 IEEE International Symposium on Performance Analysis of Systems & Software, New Brunswick, NJ, USA, April 1-3, 2012 | 7 | 0 | |
2012 | Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. | Chen, Yi-Jung; Yang, Chia-Lin; Chen, Jian-Jia; CHIA-LIN YANG | 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 | | | |
2013 | DuraCache: a durable SSD cache using MLC NAND flash. | Liu, Ren-Shuo; Yang, Chia-Lin; Li, Cheng-Hsuan; CHIA-LIN YANG | The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013 | 31 | 0 | |
2010 | Dynamic thermal management for networked embedded systems under harsh ambient temperature variation. | Park, Sangyoung; Chen, Jian-Jia; Shin, Donghwa; Kim, Younghyun; Yang, Chia-Lin; CHIA-LIN YANG | Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010 | 6 | 0 | |
2014 | EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. | Liu, Ren-Shuo; Chuang, Meng-Yen; Yang, Chia-Lin; Li, Cheng-Hsuan; Ho, Kin-Chu; CHIA-LIN YANG | The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014 | 20 | 0 | |
2008 | Energy-aware flash memory management in virtual memory system | CHIA-LIN YANG ; Li, Han-Lin; Yang, Chia-Lin; Tseng, Hung-Wei; CHIA-LIN YANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | | | |
2005 | Energy-efficient cache architecture for multimedia applications | CHIA-LIN YANG ; Yang, Chia-Lin; Lee, Chien-hao; Tseng, Hung-Wei; CHIA-LIN YANG | Emerging Information Technology Conference 2005 | | | |
1998 | Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications | CHIA-LIN YANG ; Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG | Annual International Symposium on Microarchitecture | | | |
1998 | Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. | Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG | Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998 | | | |
2013 | Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. | Lin, Ping-Sheng; Chen, Yi-Jung; Yang, Chia-Lin; YI-CHANG LU ; CHIA-LIN YANG | International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013 | 2 | 0 | |
2019 | Fair Down to the Device: A GC-Aware Fair Scheduler for SSD. | Ji, Cheng; Wang, Lun; Li, Qiao; Gao, Congming; Shi, Liang; Yang, Chia-Lin; Xue, Chun Jason; CHIA-LIN YANG | 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2019, Hangzhou, China, August 18-21, 2019 | | | |
2015 | Fine-grained write scheduling for PCM performance improvement under write power budget. | Lai, Chun-Hao; Yu, Shun-Chih; Yang, Chia-Lin; CHIA-LIN YANG | IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015 | 6 | 0 | |