公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2003 | Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder | Lian, Chung-Jr; Yang, Zhong-Lan; Chang, Hao-Chieh; Chen, Liang-Gee | IEICE Transactions on Fundamentals of Electronics | | | |
2001 | Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding | Chang, Hao-Chieh; Yang, Zhong-Lan; Lian, Chung-Jr; LIANG-GEE CHEN | ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings | 4 | 0 | |
2001 | A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform | Chen, Chien-Yu ; Yang, Zhong-Lan; Wang, Tu-Chih; Chen, Liang-Gee | The Journal of | | | |
2000 | A programmable VLSI architecture for 2-D discrete wavelet transform | Chen, Chien-Yu ; Yang, Zhong-Lan; Wang, Tu-Chih; LIANG-GEE CHEN | The IEEE International Symposium on Circuits and Systems, ISCAS 2000 Geneva. | 12 | 0 | |
2000 | Programmable VLSI architecture for 2-D discrete wavelet transform | Chen, Chien-Yu; Yang, Zhong-Lan; Wang, Tu-Chih; Chen, Liang-Gee; LIANG-GEE CHEN | IEEE International Symposium on Circuits and Systems | | | |