公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1985 | Automatic VLSI Circuit Synthesizer System Vol.1:A Programming Logic Array (PLA) Reduction and Generation System | 馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1985 | Automatic VLSI Circuit Synthesizer System Vol.2:Data Path Synthesizer | 馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1985 | Automatic VLSI Circuit Synthesizer System Vol.3:Design and Imple Mentation of a Hardware Compiler Optimizer | 馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Design and Implementation of Microprogrammed-Controller Synthesizer | 于惠中; Parng, T. P.; 馮武雄; Chen, C. F.; Sun, L. F.; Yu, Hui-Jung; Feng, Wu-Shiung | | | | |
1986 | Design and Implementation of Schematic-Entry Generation System | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Hierarchical Placement System for VLSI Design | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Hierarchical Timing Verification System for Multiple Clocked Logic Circuit | Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Feng, Wu-Shiung; Yu, Hui-Jung | 1986 Electron Devices and Materials Symposium, Tainan(1986.08) | | | |
1985 | Highly Concurrent Algorithm and Pipelined VLSI Architecture for Solving Covariance Systems | Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Yu, Hui-Jung; Feng, Wu-Shiung | International AMSE Conference on Modelling and Simulation Storrs, Connecticut(1985.07.01-07.03) | | | |
1986 | HILAS-an Hierarchical and Interactive Layout Editor System | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Integrated Entry and Verification System for VLSI Design | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Integrated VLSI Design System - Main System Design | Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1985 | Integrated VLSI Design System - MPC Chip Design | Parng, T. P.; 于惠中; 馮武雄; Lee, J. S.; Lin, S. ; Ho, H. J.; Yu, Hui-Jung; Feng, Wu-Shiung | | | | |
1985 | An Interactive Symbolic Layout System for Integrated-Circuit Design | Feng, Wu-Shiung; Yu, Hui-Jung | International Conference on CAD/CAM/CAE, Bangalore, India(1985.06) | | | |
1986 | An Interactive Symbolic Layout System for Integrated-Circuit Design - HISLID | Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1991 | A Modified Triangular Pulse Stimulator for C-Fiber Simulation | 曹偉恆; Jaw, F. S.; Yen, C. T.; 于惠中; Yu, Hui-Jung | Journal of Neuroscience | | | |
1986 | Multiple-Level Abstraction for Hierarchical VLSI Storage System | Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Netlist-Driven Cell-Layout Editor System | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Parallel Algorithm and Architecture for Solving Covariance Eigen System | Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Yu, Hui-Jung; Feng, Wu-Shiung | Advances in Modelling and Simulation, France | | | |
1986 | Private Database Management System for VLSI Design | Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1985 | A Routing Tool | Yao, H. H.; 馮武雄; 龐台銘; 于惠中; Yu, Hui-Jung | 1985 ROC Electron Devices and Materials Symposium, Hsinchu(1985.09) | | | |