Publication
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Results 1-6 of 6 (Search time: 0.004 seconds).

Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12012A fault-tolerant PE array based matrix multiplier designB.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00
22008A Self-Testing and Calibration Technique for Current-Steering DACsY.-L. Ma; J.-L. Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00
32015A Test-Application-Count Based Learning Technique for Test Time ReductionG.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00
42011Broadcast test pattern generation considering skew-insertion and partial-serial scanC.-J. Lin; J.-L. Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 30
52009Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCX.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 10
62013Improve speed path identification with suspect path expressionsJ.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00