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Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12009A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applicationsShih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU Asia and South Pacific Design Automation Conference, ASP-DAC 10
22006A novel framework for multilevel full-chip gridless routingChen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 14
32010Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimizationShih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 230
42016Cut redistribution with directed self-assembly templates for advanced 1-D gridded layoutsLin, Z.-W.; Chang, Y.-W. Asia and South Pacific Design Automation Conference, ASP-DAC 160
52009Fault Modeling and Testing of Retention Flip-Flops in Low Power DesignsB. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI Asia and South Pacific Design Automation Conference, ASP-DAC 20
62003Graph matching-based algorithms for array-based FPGA segmentation design and routingLin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 20
72006Hardware architecture design of an H.264/AVC video codecChen, T.-C.; Lian Jr.; C.; Chen, L.-G.; LIANG-GEE CHEN Asia and South Pacific Design Automation Conference, ASP-DAC 
81995Hardware-oriented design for weighted median filtersChen, Chun-Te; Chen, Liang-Gee; Hsiao, Jue-Hsuan; LIANG-GEE CHEN Asia and South Pacific Design Automation Conference, ASP-DAC 
92009High-performance global routing with fast overflow reductionQien, H.-Y.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 580
102006IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faultsLi, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 0
112004Integrating buffer planning with floorplanning for simultaneous multi-objective optimizationCheng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 8
122013Layer minimization in escape routing for staggered-pin-array PCBsHo, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 50
132004Layout techniques for on-chip interconnect inductance reductionTu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 1
141998Low power 2-D DCT chip design using direct 2-D algorithmChen, Liang-Gee; Jiu, Juing-Ying; Chang, Hao-Chieh; Lee, Yung-Pin; Ku, Chung-Wei; LIANG-GEE CHEN Asia and South Pacific Design Automation Conference, ASP-DAC 
152008LTCC spiral inductor modeling, synthesis, and optimizationChan, T.B.; Lu, H.-C.; Zeng, J.-K.; Chen, C.C.-P.; HSIN-CHIA LU Asia and South Pacific Design Automation Conference, ASP-DAC 100
162019MDP-trees: Multi-domain macro placement for ultra large-scale mixed-size designsLiu, Y.-C.; Chen, T.-C.; Chang, Y.-W. ; Kuo, S.-Y.Asia and South Pacific Design Automation Conference, ASP-DAC 20
172005Multilevel full-chip gridless routing considering optical proximity correctionChen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 20
182003Noise-aware buffer planning for interconnect-driven floorplanningLi, S.-M.; Cherng, Y.-H.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC 60
192013Power distribution network modeling for 3-D ICs with TSV arraysShen, C.-K.; Lu, Y.-C.; Chiou, Y.-P.; Cheng, T.-Y.; Wu, T.-L.; YI-CHANG LU ; TZONG-LIN WU ; YIH-PENG CHIOU Asia and South Pacific Design Automation Conference, ASP-DAC 00
202012Power optimization of wireless video sensor nodes in M2M networksChien, S.-Y.; Cheng, T.-Y.; Chiu, C.-C.; Tsung, P.-K.; Lee, C.-H.; Somayazulu, V.S.; Chen, Y.-K.; SHAO-YI CHIEN Asia and South Pacific Design Automation Conference, ASP-DAC 50