Results 1-20 of 54 (Search time: 0.008 seconds).

Issue DateTitleAuthor(s)TypescopusWOSFulltext/Archive link
12011A corner stitching compliant B-tree representation and its applications to analog placementYAO-WEN CHANG conference paper170
22013A disturb-alleviation scheme for 3D flash memoryTEI-WEI KUO conference paper240
32006A high-quality mixed-size analytical placer considering preplaced blocks and density constraintsYAO-WEN CHANG conference paper560
42005A routing algorithm for flip-chip designYAO-WEN CHANG conference paper350
52006An Adaptive Two-Level Management for the Flash Translation Layer in Embedded SystemsWu, Chin-Hsien; Kuo, Tei-Wei conference paper1180
62007An efficient algorithm for statistical circuit optimization using Lagrangian relaxationYAO-WEN CHANG conference paper20
72009An efficient pre-assignment routing algorithm for flip-chip designsYAO-WEN CHANG conference paper14
82006An optimal simultaneous diode/jumper insertion algorithm for antenna fixingYAO-WEN CHANG conference paper40
92018Analytical solution of Poisson's equation and its application to VLSI global placementZhu, W.; Huang, Z.; Chen, J.; Chang, Y.-W. Conference Paper20
102008Area-I/O flip-chip routing for chip-package co-designYAO-WEN CHANG conference paper320
112007Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic BiochipsYuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen conference paper750
122009BIST design optimization for large-scale embedded memory coresYAO-WEN CHANG conference paper7
132017Blockage-aware terminal propagation for placement wirelength minimizationYang, S.-W.; Chang, Y.-W. ; Chen, T.-C.Conference Paper00
142017Clock-aware placement for large-scale heterogeneous FPGAsKuo, Y.-C.; Huang, C.-C.; Chen, S.-C.; Chiang, C.-H.; Chang, Y.-W. ; Kuo, S.-Y.Conference Paper30
152008Constraint graph-based macro placement for modern mixed-size circuit designsYAO-WEN CHANG conference paper220
162006Current path analysis for electrostatic discharge protectionYAO-WEN CHANG conference paper70
172010Design-hierarchy aware mixed-size placement for routability optimizationYAO-WEN CHANG conference paper210
182016DSA-compliant routing for two-dimensional patterns using block copolymer lithographySu, Y.-H.; Chang, Y.-W. Conference Paper20
192007ECO timing optimization using spare cellsYAO-WEN CHANG conference paper400
202015Efficient and effective packing and analytical placement for large-scale heterogeneous FPGASYAO-WEN CHANG conference paper170