Publication
(All)

Results 1-20 of 52 (Search time: 0.043 seconds).

Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
120134-Gb/s parallel receivers with adaptive far-end crosstalk cancellationYan-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 31
220134-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrationsYan-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 00
32008A 0.18-μm CMOS 1.25-Gbps automatic-gain-control amplifierI-Hsin Wang; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 3322
42007A 0.5-5-GHz wide-range multiphase DLL with a calibrated charge pumpChi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 4541
52010A 1.62/2.7-Gb/s adaptive transmitter with two-tap preemphasis using a propagation-time detectorShih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 1010
62010A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive BiasingHuang, Mu-Chen; Liu, Shen-Iuan IEEE Transactions on Circuits and Systems II: Express Briefs 1513
72009A 10Gb/s inductorless CMOS analog equalizer with interleaved active feedback topologyJian-Hao Lu; Ke-Hou Chen; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 98
82011A 132.6GHz phase-locked loop in 65nm digital CMOSBo-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 
92011A 1~16Gb/s wide-range clock/data recovery circuit with bidirectional frequency detectorChang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 1814
102010A 20Gbps transmitter with adaptive pre-emphasis in 65nm CMOS technologyShih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 
112014A 3-25 Gb/s 4-channel receiver with noise-canceling TIA and power scalable LAYu-Hsun Chien; Kuan-Lin Fu; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 2020
122008A 3~8GHz delay-locked loop with cycle jitter calibrationChi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 139
132013A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of-252.5 dBI-Ting Lee; Kai-Hui Zeng; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 1716
142011A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithmChao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 4235
152009A 50-Gb/s 10-mW analog equalizer using transformer feedback technique in 65-nm CMOS technologyLu, Jian-Hao; Liu, Shen-Iuan IEEE Transactions on Circuits and Systems II: Express Briefs 11
162008A 50.8-53-GHz clock generator using a harmonic-locked PD in 0.13-μm CMOSChihun Lee; Lan-Chou Cho; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 87
172014A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOSTai, H.-Y.; Tsai, C.-H.; Tsai, P.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN IEEE Transactions on Circuits and Systems II: Express Briefs 1717
182007A 62.5-625MHz anti-reset all-digital delay-locked loopShao-Ku Kao; Bo-Jiun Chen; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 2317
192012A 6GHz all-digital fractional-N frequency synthesizer using FIR-embedded noise filtering techniqueI-Ting Lee; Hung-Yu Lu; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 67
202008A delay-locked loop with statistical background calibrationShao-Ku Kao; Shen-Iuan Liu; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs 66