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Issue DateTitleAuthor(s)TypescopusWOSFulltext/Archive link
120134-Gb/s parallel receivers with adaptive far-end crosstalk cancellationSHEN-IUAN LIU journal article
220134-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrationsSHEN-IUAN LIU journal article
32008A 0.18-μm CMOS 1.25-Gbps automatic-gain-control amplifierSHEN-IUAN LIU journal article
42007A 0.5-5-GHz wide-range multiphase DLL with a calibrated charge pumpSHEN-IUAN LIU journal article
52010A 1.62/2.7-Gb/s adaptive transmitter with two-tap preemphasis using a propagation-time detectorSHEN-IUAN LIU journal article
62010A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive BiasingHuang, Mu-Chen; Liu, Shen-Iuan journal article
72009A 10Gb/s inductorless CMOS analog equalizer with interleaved active feedback topologyLu, Jian-Hao; SHEN-IUAN LIU ; Chen, Ke-Hou; Liu, Shen-Iuan journal article
82011A 132.6GHz phase-locked loop in 65nm digital CMOSSHEN-IUAN LIU journal article
92011A 1~16Gb/s wide-range clock/data recovery circuit with bidirectional frequency detectorSHEN-IUAN LIU journal article
102010A 20Gbps transmitter with adaptive pre-emphasis in 65nm CMOS technologySHEN-IUAN LIU journal article
112014A 3-25 Gb/s 4-channel receiver with noise-canceling TIA and power scalable LASHEN-IUAN LIU journal article
122008A 3~8GHz delay-locked loop with cycle jitter calibrationSHEN-IUAN LIU journal article
132013A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of-252.5 dBSHEN-IUAN LIU journal article
142011A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithmSHEN-IUAN LIU journal article
152009A 50-Gb/s 10-mW analog equalizer using transformer feedback technique in 65-nm CMOS technologyLu, Jian-Hao; Liu, Shen-Iuan journal article
162008A 50.8-53-GHz clock generator using a harmonic-locked PD in 0.13-μm CMOSSHEN-IUAN LIU journal article
172014A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOSHSIN-SHU CHEN journal article
182007A 62.5-625MHz anti-reset all-digital delay-locked loopSHEN-IUAN LIU journal article
192012A 6GHz all-digital fractional-N frequency synthesizer using FIR-embedded noise filtering techniqueSHEN-IUAN LIU journal article
202008A delay-locked loop with statistical background calibrationSHEN-IUAN LIU journal article