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Results 1-11 of 11 (Search time: 0.006 seconds).

Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
120033-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuitsJ. Kim; LIANG-HUNG LU et al. Symposium on VLSI Circuits 290
22007A 0.5-V 1.9-GHz low-power phase-locked loop in 0.18-μm CMOSH.-H. Hsieh; C.-T. Lu; L.-H. Lu; LIANG-HUNG LU Symposium on VLSI Circuits 320
32009A 132.7-to-143.5GHz injection-locked frequency divider in 65nm CMOSBo-Yu Lin; Shen-Iuan Liu; SHEN-IUAN LIU Symposium on VLSI Circuits 8
42005A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-μm CMOS technologyJri Lee; Jian-yu Ding; Tuan-yi Cheng; JRI LEE Symposium on VLSI Circuits 130
52006A 40-GHz wide-tuning-range VCO in 0.18-um CMOSJ.-C. Chien; L.-H. Lu; LIANG-HUNG LU Symposium on VLSI Circuits 00
62011A 40Gb/s adaptive receiver with linear equalizer and merged DFE/CDRChang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU Symposium on VLSI Circuits 5
72009A 40Gb/s decision feedback equalizer using back-gate feedback techniqueChang-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU Symposium on VLSI Circuits 12
82007A 63-GHz voltage-controlled oscillator in 0.18-μm CMOSH.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU Symposium on VLSI Circuits 180
92006A 9.5-dB 50-GHz Matrix Distributed Amplifier in 0.18-μm CMOSJ.-C. Chien; T.-Y. Chen; L.-H. Lu; LIANG-HUNG LU Symposium on VLSI Circuits 130
102007A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current TuningK-J Hsiao; T-C Lee; TAI-CHENG LEE Symposium on VLSI Circuits 40
112005Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS TechnologyJri Lee; Shanghann Wu; JRI LEE Symposium on VLSI Circuits 40