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Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12010A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engineCheng, C.-C.; Tsai, Y.-M.; Chen, L.-G.; Ch; rakasan, A.P.; LIANG-GEE CHEN Custom Integrated Circuits Conference 70
21997Design and implementation of a highly efficient VLSI architecture for discrete wavelet transformYu, Chu; Hsieh, Chien-An; Chen, Sao-Jie Custom Integrated Circuits Conference 00
31995Efficient approach for via minimization in multi-layer VLSI/PCB routingCherng, Jong-Sheng; Chen, Sao-Jie; Tsai, Chia-Chun; Ho, Jan-Ming; SAO-JIE CHEN Custom Integrated Circuits Conference 
41993Efficient signal redistribution algorithm for MCMShiao, Ming-Fu; Changfan, Chieh; Chen, Sao-Jie; Tsai, Chia-Chun; SAO-JIE CHEN Custom Integrated Circuits Conference 
51991Hybrid routing on multichip modulesTsai, Chia-Chun; Chen, Sao-Jie ; Hsiao, Pei-Yung; Feng, Wu-ShiungCustom Integrated Circuits Conference 00
62011ReSSP: A 5.877 TOPS/W reconfigurable smart-camera stream processorChan, W.-K.; Tseng, Y.-H.; Tsung, P.-K.; Chuang, T.-D.; Tsai, Y.-M.; Chen, W.-Y.; Chen, L.-G.; Chien, S.-Y.; LIANG-GEE CHEN ; SHAO-YI CHIEN Custom Integrated Circuits Conference 30
71999Single chip CMOS APS camera with direct frame difference outputMa, Shyh-Yih; Chen, Liang-Gee; LIANG-GEE CHEN Custom Integrated Circuits Conference 
81996Stable partitioning algorithm for VLSI circuitsCherng, Jong-Sheng; Chen, Sao-Jie; SAO-JIE CHEN Custom Integrated Circuits Conference 
92009Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysisChen, T.-W.; Tang, C.-S.; Tsai, S.-F.; Tsai, C.-H.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; SHAO-YI CHIEN Custom Integrated Circuits Conference 10