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Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
11999A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially Depleted SOI Dynamic-Threshold TechniqueS. C. Liu; J. B. Kuo; JAMES-B KUO IEEE International SOI Conference Proceedings 00