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Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12023Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAsWei, Min; Tong, Xingyu; Wen, Yuan; Chen, Jianli; Yu, Jun; Zhu, Wenxing; YAO-WEN CHANG ACM Transactions on Design Automation of Electronic Systems00
22023Security-Aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection AttacksHsu, Jhih Wei; Chen, Kuan Cheng; Chen, Yan Syuan; Lo, Yu Hsiang; YAO-WEN CHANG Proceedings of the International Symposium on Physical Design00
32023A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology DesignsChen, Yan Lin; Tseng, Wei Che; Kao, Wei Yao; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
42023Floorplanning for Embedded Multi-Die Interconnect Bridge PackagesLee, Chung Chia; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
52023PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy ExplorationCai, Zhijie; Zou, Peng; Wu, Zhengtao; Tong, Xingyu; Yu, Jun; Chen, Jianli; YAO-WEN CHANG Proceedings - Design Automation Conference00
62023A Matching Based Escape Routing Algorithm with Variable Design Rules and ConstraintsLiu, Qinghai; Lin, Disi; Chen, Chuandong; He, Huan; Chen, Jianli; YAO-WEN CHANG Proceedings - Design Automation Conference00
72023Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing TechnologiesChen, Yan Jen; Chen, Yan Syuan; Tseng, Wei Che; Chiang, Cheng Yu; Lo, Yu Hsiang; YAO-WEN CHANG Proceedings - Design Automation Conference00
82023Any-Angle Routing for Redistribution Layers in 2.5D IC PackagesChung, Min Hsuan; Chuang, Je Wei; YAO-WEN CHANG Proceedings - Design Automation Conference00
92023Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected CircuitsTseng, Wei Hsiang; YAO-WEN CHANG Proceedings - Design Automation Conference00
102023Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC DesignsChen, Kuan Cheng; Chen, Yan Lin; Lu, Yu Sheng; YAO-WEN CHANG Proceedings - Design Automation Conference00
112023Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly TechnologyChen, Wei Hsu; YAO-WEN CHANG Proceedings - Design Automation Conference00
122023Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex ConstraintsLiu, Qinghai; Tang, Qinfei; Chen, Jiarui; Chen, Chuandong; Zhu, Ziran; He, Huan; Chen, Jianli; YAO-WEN CHANG Proceedings - Design Automation Conference00
132023High-performance Placement Engine for Modern Large-scale FPGAs With Heterogeneity and Clock ConstraintsZhu, Ziran; Mei, Yangjie; Deng, Kangkang; He, Huan; Chen, Jianli; Yang, Jun; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems0
142022SGIRR: Sparse graph index remapping for ReRAM crossbar operation unit and power optimizationWang, Cheng Yuan; YAO-WEN CHANG ; Chang, Yuan HaoIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD00
152022Obstacle-avoiding multiple redistribution layer routing with irregular structuresChen, Yen Ting; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD00
162022Transitive closure graph-based warpage-aware floorplanning for package designsHsu, Yang; Chung, Min Hsuan; YAO-WEN CHANG ; Lin, Ci HongIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD00
172022Late Breaking Results: Subgraph Matching Based Reference Placement for PCB DesignsSu, Miaodi; Xiao, Yifeng; Zhang, Shu; Su, Haiyuan; Xu, Jiacen; He, Huan; Zhu, Ziran; Chen, Jianli; YAO-WEN CHANG Proceedings - Design Automation Conference00
182022Late Breaking Results: Flexible Chip Placement via Reinforcement LearningChang, Fu Chieh; Tseng, Yu Wei; Yu, Ya Wen; Lee, Ssu Rui; Cioba, Alexandru; Tseng, I. Lun; Shiu, Da Shan; Hsu, Jhih Wei; Wang, Cheng Yuan; Yang, Chien Yi; Wang, Ren Chu; YAO-WEN CHANG ; Chen, Tai Chen; Chen, Tung ChiehProceedings - Design Automation Conference00
192022A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuitsTseng, Wei Hsiang; YAO-WEN CHANG Proceedings - Design Automation Conference10
202022High-performance placement for large-scale heterogeneous FPGAs with clock constraintsZhu, Ziran; Mei, Yangjie; Li, Zijun; Lin, Jingwen; Chen, Jianli; Yang, Jun; YAO-WEN CHANG Proceedings - Design Automation Conference20
212022Y-architecture-based flip-chip routing with dynamic programming-based bend minimizationNie, Szu Ru; Chen, Yen Ting; YAO-WEN CHANG Proceedings - Design Automation Conference10
222022Thermal-aware optical-electrical routing codesign for on-chip signal communicationsLu, Yu Sheng; Chen, Kuan Cheng; Hsu, Yu Ling; YAO-WEN CHANG Proceedings - Design Automation Conference00
232022CNN-inspired analytical global placement for large-scale heterogeneous FPGAsWang, Huimin; Tong, Xingyu; Ma, Chenyue; Shi, Runming; Chen, Jianli; Wang, Kun; Yu, Jun; YAO-WEN CHANG Proceedings - Design Automation Conference20
242022Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad StructuresWen H; Cai Y; Hsu Y; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10
252022High-Correlation 3D Routability Estimation for Congestion-guided Global RoutingSu M; Ding H; Weng S; Zou C; Zhou Z; Chen Y; Chen J; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC40
262022Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask VerificationBai X; Zhu Z; Zou P; Chen J; Yu J; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC00
272022A Bridge-based Compression Algorithm for Topological Quantum CircuitsTseng W; Hsu C; Lin W; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
282022Mixed-Cell-Height Placement with Drain-to-Drain Abutment and Region ConstraintsChen J; Zhu Z; Guo L; Tseng Y; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems32
292021Simultaneous Pre-and Free-assignment Routing for Multiple Redistribution Layers with Irregular ViasCai Y.-J; Hsu Y; YAO-WEN CHANG Proceedings - Design Automation Conference40
302021Opportunities for 2.5/3D Heterogeneous SoC IntegrationCHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings10
312021A Row-Based Algorithm for Non-Integer Multiple-Cell-Height PlacementLin Z.-Y; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD20
322021VLSI Structure-aware Placement for Convolutional Neural Network Accelerator UnitsChou Y; Hsu J.-W; Chen T.-C.; YAO-WEN CHANG Proceedings - Design Automation Conference30
332021Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA SystemsChen M.-H; Wang J.-J.; YAO-WEN CHANG Proceedings - Design Automation Conference50
342021Topological Structure and Physical Layout Co-design for Wavelength-Routed Optical Networks-on-ChipLu Y; Chen Y; Yu S; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems22
352021Timing-Aware Fill Insertions with Design-Rule and Density ConstraintsBai X; Zhu Z; Li P; Chen J; Lan T; Li X; Yu J; Zhu W; Chang Y.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
362021Time-Division Multiplexing Based System-Level FPGA RoutingLiu W.-K; Chen M.-H; Chang C.-M; Chang C.-C; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD00
372021Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot DetectionWang B; Jiang L; Zhu W; Guo L; Chen J; YAO-WEN CHANG Proceedings - Design Automation Conference10
382021On-Chip Optical Routing with Provably Good Algorithms for Path Clustering and AssignmentLu Y; Yu S; Chang Y.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
392021A Bridge-based Compression Algorithm for Topological Quantum CircuitsHsu C.-H; Lin W.-H; Tseng W.-H; YAO-WEN CHANG Proceedings - Design Automation Conference20
402021On-chip Optical Routing with Waveguide Matching ConstraintsChuang F.-Y; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD10
412021A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit LegalizationChen J; Zhu Z; Zhu W; YAO-WEN CHANG ACM Transactions on Design Automation of Electronic Systems76
422021Analytical Placement Considering the Electron-Beam Fogging EffectChen J; Chang Y.-W; Huang Y.-C.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems33
432021A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus RoutingHsu C.-H; Hung S.-C; Chen H; Sun F.-K; Chang Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems42
442020Intelligent Design Automation for 2.5/3D Heterogeneous SoC IntegrationJiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD50
452020高功率直驅式半導體雷射之發展宋育誠; 蘇信嘉; 張耀文; 林士廷; YAO-WEN CHANG 機械工業雜誌
462020Routability-Aware Pin Access Optimization for Monolithic 3D Designs*Wang R.-Y; Chang Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD00
472020Mixed-Cell-Height Legalization Considering Technology and Region ConstraintsZhu Z; Chen J; Zhu W; Chang Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems88
482020Unified Redistribution Layer Routing for 2.5D IC PackagesChiang, C.-H.; Chuang, F.-Y.; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC20
492020Time-division multiplexing based system-level FPGA routing for logic verificationZou, P.; Lin, Z.; Shi, X.; Wu, Y.; Chen, J.; Yu, J.; YAO-WEN CHANG Proceedings - Design Automation Conference50
502020An efficient EPIST algorithm for global placement with non-integer multiple-height cellsChen, J.; Huang, Z.; Huang, Y.; Zhu, W.; Yu, J.; YAO-WEN CHANG Proceedings - Design Automation Conference30
512020Hamiltonian path based mixed-cell-height legalization for neighbor diffusion effect mitigationChen, J.; Zhu, Z.; Liu, Q.; Zhang, Y.; Zhu, W.; YAO-WEN CHANG Proceedings - Design Automation Conference40
522020A provably good wavelength-division-multiplexing-aware clustering algorithm for on-chip optical routingLu, Y.-S.; Yu, S.-J.; YAO-WEN CHANG Proceedings - Design Automation Conference60
532020Topological structure and physical layout codesign for wavelength-routed optical networks-on-chipLu, Y.-S.; Yu, S.-J.; YAO-WEN CHANG Proceedings - Design Automation Conference60
542020Via-based redistribution layer routing for InFO packages with irregular pad structuresWen, H.-T.; Cai, Y.-J.; Hsu, Y.; YAO-WEN CHANG Proceedings - Design Automation Conference70
552020Latch clustering for timing-power co-optimizationHuang, C.-C.; Tellez, G.; Nam, G.-J.; YAO-WEN CHANG Proceedings - Design Automation Conference20
562020Clock-Aware Placement for Large-Scale Heterogeneous FPGAsChen, J.; Lin, Z.; Kuo, Y.; Huang, C.; Chang, Y.; Chen, S.; Chiang, C.; SY-YEN KUO ; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1411
572019MDP-trees: Multi-Domain Macro Placement for Ultra Large-Scale Mixed-Size DesignsY. C. Liu; T. C. Chen; Y. W. Chang; S. Y. Kuo; Chang, Y.-W. 24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019)40
582019Many-body theory of optical absorption in doped two-dimensional semiconductorsChang, Y.-W.; Reichman, D.R.; YAO-WEN CHANG Physical Review B2523
592019Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging.Chen, Dar-Ren; Chang, Yao-Wen; Wu, Hwa-Koon; Shia, Wei-Chung; Huang, Yu-Len; YAO-WEN CHANG J. Digital Imaging54
602019DSA-Compliant Routing for 2-D Patterns Using Block Copolymer LithographySu, Y.-H.; Chang, Y.-W. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
612019Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.Alioto, Massimo; Abadir, Magdy S.; Arslan, Tughrul; Boon, Chirn Chye; Burg, Andreas; Chang, Chip-Hong; Chang, Meng-Fan; Chen, Poki; Corsonello, Pasquale; Crovetti, Paolo; Dosho, Shiro; Drechsler, Rolf; Elfadel, Ibrahim Abe M.; Han, Ruonan; Hashimoto, Masanori; Heng, Chun-Huat; Heo, Deukhyoun; Ho, Tsung-Yi; Homayoun, Houman; Hwang, Yuh-Shyan; Joshi, Ajay; Joshi, Rajiv V.; Karnik, Tanay; Kim, Chulwoo; Kim, Tae-Hyoung; Kulkarni, Jaydeep; Kursun, Volkan; Lee, Yoonmyung; Li, Hai Helen; Li, Huawei; Mishra, Prabhat; Mohammad, Baker; Kermani, Mehran Mozaffari; Nagata, Makoto; Nii, Koji; Pande, Partha Pratim; Paul, Bipul C.; Pavlidis, Vasilis F.; Gyvez, Jos? Pineda de; Savidis, Ioannis; Schaumont, Patrick; Sebastiano, Fabio; Sengupta, Anirban; Seok, Mingoo; Stan, Mircea R.; Tehranipoor, Mark M.; Todri-Sanial, Aida; Verhelst, Marian; Vignoli, Valerio; Wen, Xiaoqing; Xu, Jiang; Zhang, Wei; Zhang, Zhengya; Zhou, Jun; Zwolinski, Mark; Weber, Stacey; YAO-WEN CHANG IEEE Trans. VLSI Syst.66
622019Analytical Mixed-cell-height legalization considering average and maximum movement minimizationLi, X.; Chen, J.; Zhu, W.; Chang, Y.-W.; YAO-WEN CHANG Proceedings of the International Symposium on Physical Design140
632019A DAG-based algorithm for obstacle-aware topology-matching on-track bus routingHsu, C.-H.; Hungz, S.-C.; Chenz, H.; Sunz, F.-K.; Chang, Y.-W.; YAO-WEN CHANG Proceedings - Design Automation Conference10
642019A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing.Hsu, Chen-Hao; Hung, Shao-Chun; Chen, Hao; Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 201900
652019BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement.Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 201900
662019BiG: A bivariate gradient-based wirelength model for analytical circuit placementSunl, F.-K.; Chang, Y.-W.; YAO-WEN CHANG Proceedings - Design Automation Conference50
672019Analytical placement with 3D poisson's equation and ADMM based optimization for large-scale 2.5D heterogeneous FPGAsChen J; Zhu W; Yu J; He L; Chang Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD20
682019Timing-aware fill insertions with design-rule and density constraintsLan T; Li X; Chen J; Yu J; He L; Dong S; Zhu W; Chang Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD20
692019Obstacle-aware group-based length-matching routing for pre-assignment area-I/O flip-chip designsChang, Y.-H.; Wen, H.-T.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD30
702019Graph-and ILP-based cut redistribution for two-dimensional directed self-assemblyWang, Z.-L.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD10
712018NTU place4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs with Technology and Region ConstraintsHuang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C.; Bustany, I.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems3431
722018Generalized augmented lagrangian and its applications to VLSI global placementZhu, Z.; Chen, J.; Peng, Z.; Zhu, W.; Chang, Y.-W. Design Automation Conference150
732018WB-trees: A meshed tree representation for FinFET analog layout designsLu, Y.-S.; Chang, Y.-H.; Chang, Y.-W. Design Automation Conference80
742018Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree constructionWang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI Design Automation Conference50
752018DSA-Friendly detailed routing considering double patterning and DSA template assignmentsYu, H.-J.; Chang, Y.-W. Design Automation Conference60
762018Provably good max–min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabricationLin Z.-W; Fang S.-Y; Chang Y.-W; Rao W.-C; CHIEH-HSIUNG KUAN ; Chang, Y.-W. IEEE Transactions on Very Large Scale Integration (VLSI) Systems22
772018A multithreaded initial detailed routing algorithm considering global routing guidesSun, F.-K.; Chen, H.; Chen, C.-Y.; Hsu, C.-H.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design230
782018Mixed-cell-height legalization considering technology and region constraintsZhu, Z.; Li, X.; Chen, Y.; Chen, J.; Zhu, W.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design140
792018Mixed-cell-height placement considering drain-to-drain abutmentTseng, Y.-W.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design110
802018Novel proximal group ADMM for placement considering fogging and proximity effectsChen, J.; Yang, L.; Peng, Z.; Zhu, W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design80
812018Analytical solution of Poisson's equation and its application to VLSI global placementZhu, W.; Huang, Z.; Chen, J.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design130
822018Polarized excitons and optical activity in single-wall carbon nanotubesChang, Y.-W. ; Jin, B.-Y.Physical Review B11
832018beta-Nitrostyrene derivatives attenuate LPS-mediated acute lung injury via the inhibition of neutrophil-platelet interactions and NET releaseChang, Yao-Wen; Tseng, Ching-Ping; Lee, Chih-Hsun; Hwang, Tsong-Long; Chen, Yu-Li; Su, Mei-Tzu; Chong, Kowit-Yu; Lan, Ying-Wei; Wu, Chin-Chung; Chen, Kung-Ju; Lu, Fen-Hua; Liao, Hsiang-Ruei; Hsueh, Chuen; Hsieh, Pei-Wen; YAO-WEN CHANG American Journal of Physiology-Lung Cellular and Molecular Physiology109
842018Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systemsChen, S.-C.; Sun, R.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD160
852018Mixed-cell-height placement with complex minimum-implant-area constraintsChen, J.; Yang, P.; Li, X.; Zhu, W.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design150
862017Generalized force directed relaxation with optimal regions and its applications to circuit placementChang, Y.-W. International Symposium on Physical Design10
872017FPGA placement and routingChen, S.-C.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design160
882017Nanowire-Aware Routing Considering High Cut Mask ComplexitySu, Y.-H.; Chang, Y.-W. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10
892017An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designsChen, S.-T.; Chang, Y.-W. ; Chen, T.-C.IEEE/ACM International Conference on Computer-Aided Design40
902017Toward Optimal Legalization for Mixed-Cell-Height Circuit DesignsChen, J.; Zhu, Z.; Zhu, W.; Chang, Y.-W. Design Automation Conference380
912017Fogging Effect Aware Placement in Electron Beam LithographyHuang, Y.-C.; Chang, Y.-W. Design Automation Conference70
922017Graph-Based Logic Bit Slicing for Datapath-Aware PlacementHuang, C.-C.; Lin, B.-Q.; Lee, H.-Y.; Chang, Y.-W. ; Wu, K.-S.; Yang, J.-Z.Design Automation Conference70
932017Blockage-aware terminal propagation for placement wirelength minimizationYang, S.-W.; Chang, Y.-W. ; Chen, T.-C.IEEE/ACM International Conference on Computer-Aided Design00
942017Detailed Placement for Two-Dimensional Directed Self-Assembly TechnologyLin, Z.-W.; Chang, Y.-W. Design Automation Conference30
952017Mixed-cell-height detailed placement considering complex minimum-implant-area constraintsWu, Y.-Y.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design170
962017Redistribution layer routing for wafer-level integrated fan-out package-on-packagesLin, T.-C.; Chi, C.-C.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design90
972017A novel damped-wave framework for macro placementChang, C.-H.; Chang, Y.-W. ; Chen, T.-C.IEEE/ACM International Conference on Computer-Aided Design120
982017Cut Redistribution with Directed-Self-Assembly Templates for Advanced 1-D Gridded LayoutsLin, Z.-W.; Chang, Y.-W. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
992017Clock-aware placement for large-scale heterogeneous FPGAsKuo, Y.-C.; Huang, C.-C.; Chen, S.-C.; Chiang, C.-H.; Chang, Y.-W. ; Kuo, S.-Y.IEEE/ACM International Conference on Computer-Aided Design120
1002017Theory of charge transport in molecular junctions: Role of electron correlationChang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG Journal of Chemical Physics22
1012017An Interview With Professor Chenming Hu, Father of 3D TransistorsChang, Yao-Wen; Hu, Chenming; YAO-WEN CHANG Ieee Design & Test00
1022017Editorial.Chakrabarty, Krishnendu; Alioto, Massimo; Baas, Bevan M.; Boon, Chirn Chye; Chang, Meng-Fan; Chang, Naehyuck; Chang, Yao-Wen; Chang, Chip-Hong; Chang, Shih-Chieh; Chen, Poki; Chowdhury, Masud H.; Corsonello, Pasquale; Elfadel, Ibrahim Abe M.; Hamdioui, Said; Hashimoto, Masanori; Ho, Tsung-Yi; Homayoun, Houman; Hwang, Yuh-Shyan; Joshi, Rajiv V.; Karnik, Tanay; Kermani, Mehran Mozaffari; Kim, Chulwoo; Kim, Tae-Hyoung; Kulkarni, Jaydeep P.; Kursun, Eren; Larsson, Erik; Li, Hai (Helen); Li, Huawei; Mercier, Patrick P.; Mishra, Prabhat; Nagata, Makoto; Natarajan, Arun S.; Nii, Koji; Pande, Partha Pratim; Savidis, Ioannis; Seok, Mingoo; Tan, Sheldon X.-D.; Tehranipoor, Mark Mohammad; Todri-Sanial, Aida; Velev, Miroslav N.; Wen, Xiaoqing; Xu, Jiang; Zhang, Wei; Zhang, Zhengya; Jackson, Stacey Weber; YAO-WEN CHANG IEEE Trans. VLSI Syst.00
1032017An effective legalization algorithm for mixed-cell-height standard cellsWang, C.-H.; Wu, Y.-Y.; Chen, J.; Chang, Y.-W.; Kuo, S.-Y.; Zhu, W.; SY-YEN KUO ; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC400
1042017Pool-boiling heat-transfer enhancement on cylindrical surfaces with hybrid wettable patternsKumar C. S.; S.; Chang, Y.W.; PING-HEI CHEN ; YAO-WEN CHANG Journal of Visualized Experiments1612
1052017Effect of heterogeneous wettable structures on pool boiling performance of cylindrical copper surfacesSujith Kumar, C.S.; Chang, Y.W. ; PING-HEI CHEN Applied Thermal Engineering6056
1062016Timing-Driven Cell Placement Optimization for Early Slack Histogram CompressionC. C. Huang; Y. C. Liu; Y. S. Lu; Y. C. Kuo; Y. W. Chang; S. Y. Kuo; SY-YEN KUO ; YAO-WEN CHANG 53th ACM/IEEE Design Automation Conference (DAC-2016)90
1072016Cut redistribution with directed self-assembly templates for advanced 1-D gridded layoutsLin, Z.-W.; Chang, Y.-W. Asia and South Pacific Design Automation Conference, ASP-DAC160
1082016DSA-compliant routing for two-dimensional patterns using block copolymer lithographySu, Y.-H.; Chang, Y.-W. IEEE/ACM International Conference on Computer-Aided Design40
1092016Recent research development and new challenges in analog layout synthesisLin, M.P.-H.; Chang, Y.-W.; Hung, C.-M.; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC430
1102016QB-trees: Towards an optimal topological representation and its applications to analog layout designsWu, I.-P.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference120
1112016Detailed-routability-driven analytical placement for mixed-size designs with technology and region constraintsHuang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015170
1122016Double-patterning aware DSA template guided cut redistribution for advanced 1-D gridded designsLin, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design180
1132016Layout-Dependent Effects-Aware Analytical Analog PlacementOu, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4437
1142016Circular-contour-based obstacle-aware macro placementChiou, C.-H.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC140
1152016Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut ProcessLiu, Iou-Jen; Fang, Shao-Yun; Chang, Yao-Wen; YAO-WEN CHANG Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems65
1162016VCR: Simultaneous via-template and cut-template-aware routing for directed self-assembly technologySu, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD40
1172016Redistribution layer routing for integrated fan-out wafer-level chip-scale packagesLin, B.-Q.; Lin, T.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD120
1182016Provably good max-min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabricationLin, Z.-W.; Fang, S.-Y.; Chang, Y.-W.; Rao, W.-C.; CHIEH-HSIUNG KUAN ; YAO-WEN CHANG ; Chang, Y.-W. 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 201510
1192016Fast lithographic mask optimization considering process variationSu, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems3430
1202016Minimum-implant-area-aware detailed placement with spacing constraintsTseng, K.-H.; Chang, Y.-W.; Liu, C.C.C.; YAO-WEN CHANG Design Automation Conference180
1212016Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummificationChiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems54
1222015Detailed-Routing-Driven analytical standard-cell placementHuang, C.-C.; Chiou, C.-H.; Tseng, K.-H.; Chang, Y.-W.; YAO-WEN CHANG 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015180
1232015Stitch-aware routing for multiple e-beam lithographyLiu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems66
1242015Layout-dependent-effects-aware analytical analog placementOu, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference150
1252015ForewordChang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design00
1262015Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuitsHo, K.-H.; Ou, H.-C.; Chang, Y.-W.; Tsao, H.-F.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1211
1272015EUV and e-beam manufacturability: Challenges and solutionsChang, Y.-W.; Liu, R.-G.; Fang, S.-Y.; YAO-WEN CHANG Design Automation Conference150
1282015Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithographyOu, H.-C.; Tseng, K.-H.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference20
1292015Nanowire-aware routing considering high cut mask complexitySu, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference110
1302015Identification of a novel platelet antagonist that binds to CLEC-2 and suppresses podoplanin-induced platelet aggregation and cancer metastasisChang, Yao-Wen; Hsieh, Pei-Wen; Chang, Yu-Tsui; Lu, Meng-Hong; TUR-FU HUANG ; Chong, Kowit-Yu; Liao, Hsiang-Ruei; Cheng, Ju-Chien; YAO-WEN CHANG Oncotarget7462
1312015Efficient and effective packing and analytical placement for large-scale heterogeneous FPGASChen, Y.-C.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design270
1322015Non-stitch triple patterning-aware routing based on conflict graph pre-coloringHsu, P.-Y.; Chang, Y.-W.; YAO-WEN CHANG 20th Asia and South Pacific Design Automation Conference, ASP-DAC 201580
1332015Routing-architecture-aware analytical placement for heterogeneous FPGASChen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference180
1342015Fast lithographic mask optimization considering process variationSu, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design90
1352015Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterningFang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG 20th Asia and South Pacific Design Automation Conference, ASP-DAC 201570
1362014Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware DummificationChi-Yuan Liu; Hui-Ju K. Chiang; Yao-Wen Chang; Jie-Hong R. Jiang; YAO-WEN CHANG ; JIE-HONG JIANG ACM/IEEE Design Automation Conference (DAC)40
1372014The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014YAO-WEN CHANG 
1382014NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designsHsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chou, S.; Lin, T.-H.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems5351
1392014Simultaneous EUV flare- and CMP-aware placementLiu, C.-Y.; Chang, Y.-W.; YAO-WEN CHANG 2014 32nd IEEE International Conference on Computer Design, ICCD 201450
1402014Routability-driven blockage-aware macro placementChen, Y.-F.; Huang, C.-C.; Chiou, C.-H.; Wang, C.-J.; YAO-WEN CHANG Design Automation Conference180
1412014Functional ECO using metal-configurable gate-array spare cellsChang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG Design Automation Conference10
1422014A novel layout decomposition algorithm for triple patterning lithographyFang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4643
1432014Theory of charge transport in molecular junctions: From Coulomb blockade to coherent tunnelingChang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG Journal of Chemical Physics44
1442014Overlay-Aware detailed routing for self-Aligned double patterning lithography using the cut processLiu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference250
1452014Design and Implementation of a RESTful Notification Service.Chang, Yao-Wen; Sheu, Ruey-Kai; Jhu, Syuan-Ru; Chang, Yue-Shan; YAO-WEN CHANG Intelligent Systems and Applications - Proceedings of the International Computer Symposium (ICS) held at Taichung, Taiwan, December 12-14, 201400
1462014Nonuniform multilevel analog routing with matching constraintsOu, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2218
1472014A new asynchronous pipeline template for power and performance optimizationHo, K.-H.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference80
1482014Buffered clock tree synthesis considering self-heating effectsLin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Low Power Electronics and Design10
1492014Obstacle-avoiding free-assignment routing for flip-chip designsHo, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems99
1502014Buffered clock tree synthesis considering self-heating effects.Lin, Chung-Wei; Hsu, Tzu-Hsuan; Shih, Xin-Wei; YAO-WEN CHANG ; CHUNG-WEI LIN International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 201400
1512013Numerical and experimental investigation of polycarbonate vacuum-forming processChang, Y.-W.; JUNG-HO CHENG ; YAO-WEN CHANG Journal of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an66
1522013Stitch-aware routing for multiple e-beam lithographyFang, S.-Y.; Liu, I.-J.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference90
1532013Layer minimization in escape routing for staggered-pin-array PCBsHo, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC50
1542013Simultaneous analog placement and routing with current flow and current density considerationsOu, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference280
1552013Routability-driven placement for hierarchical mixed-size circuit designsHsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference270
1562013Technical perspective: Circuit placement challengesChang, Y.-W.; YAO-WEN CHANG Communications of the ACM22
1572013TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength modelHsu, M.-K.; Balabanov, V.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems6854
1582013Coupling-Aware length-ratio-matching routing for capacitor arrays in analog integrated circuitsHo, K.-H.; Ou, H.-C.; Tsao, H.-F.; YAO-WEN CHANG Proceedings - Design Automation Conference60
1592013Double patterning lithography-aware analog placementChien, H.-C.C.; Ou, H.-C.; Chen, T.-C.; Kuan, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference80
1602013An efficient and effective analytical placer for FPGAsLin, T.-H.; Banerjee, P.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference360
1612013Graph-based subfield scheduling for electron-beam photomask fabricationFang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems87
1622013Multiple chip planning for chip-interposer codesignHo, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference280
1632013Escape routing for staggered-pin-array PCBsHo, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1211
1642013Symmetrical buffered clock-tree synthesis with supply-voltage alignmentShih, X.-W.; Hsu, T.-H.; Lee, H.-C.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC40
1652013ECO optimization using metal-configurable gate-array spare cellsChang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems22
1662013Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling.Fang, Shao-Yun; Lin, Chung-Wei; Liao, Guang-Wan; YAO-WEN CHANG ; CHUNG-WEI LIN International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 201340
1672012Material characterization of polycarbonate near glass transition temperatureJUNG-HO CHENG ; YAO-WEN CHANG Journal of the Chinese Institute of Engineers, Series A/Chung-kuo Kung Ch'eng Hsuch K'an22
1682012Unified analytical global placement for large-scale mixed-size circuit designsHsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1919
1692012Non-uniform multilevel analog routing with matching constraintsOu, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference240
1702012Obstacle-avoiding free-assignment routing for flip-chip designsLee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG Design Automation Conference20
1712012TRECO: Dynamic technology remapping for timing engineering change ordersHo, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems88
1722012Statistical thermal modeling and optimization considering leakage power variationsJuan, D.-C.; Chuang, Y.-L.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG Design, Automation and Test in Europe, DATE10
1732012A novel layout decomposition algorithm for triple patterning lithographyFang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG Design Automation Conference470
1742012Structure-aware placement for datapath-intensive circuit designsChou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference310
1752012Native-conflict and stitch-aware wire perturbation for double patterning technologyFang, S.-Y.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2016
1762012Simultaneous flare level and flare variation minimization with dummification in EUVLFang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference140
1772012Fast timing-model independent buffered clock-tree synthesisShih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1410
1782012Correlation effects of πelectrons on the band structures of conjugated polymers using the self-consistent GW approximation with vertex correctionsChang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG Journal of Chemical Physics77
1792012Statistical thermal modeling and optimization considering leakage power variations.Juan, Da-Cheng; Chuang, Yi-Lin; Marculescu, Diana; Chang, Yao-Wen; YAO-WEN CHANG 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 201200
1802012Self-interaction correction to GW approximationChang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG Physica Scripta44
1812012A chip-package-board co-design methodologyLee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference40
1822012Graph-based subfield scheduling for electron-beam photomask fabricationFang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design30
1832012An Efficient Pre-assignment Routing Algorithm for Flip-Chip DesignsLin, Chung-Wei; Lee, Po-Wei; Chang, Yao-Wen; Shen, Chin-Fang; YAO-WEN CHANG ; CHUNG-WEI LIN Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems1614
1842012Timing ECO optimization via B?zier curve smoothing and fixability identificationChang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems119
1852012Timing ECO optimization using metal-configurable gate-array spare cellsChang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG Proceedings - Design Automation Conference40
1862011Simultaneous functional and timing ECOChang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference17
1872011Heterogeneous B*-trees for analog placement with symmetry and regularity considerationsChou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design260
1882011Simultaneous layout migration and decomposition for double patterning technologyHsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1917
1892011Pulsed-latch aware placement for timing-integrity optimizationChuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems31
1902011A corner stitching compliant B-tree representation and its applications to analog placementTsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design230
1912011An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage applicationWang, S.-Y.; Chang, Y.-W.; Chen, Y.-Y.; He, C.-W.; Wu, G.-W.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG IEEE International Reliability Physics Symposium20
1922011IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest EditorialSaxena, P.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
1932011PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designsChuang, Y.-L.; Lin, H.-T.; Ho, T.-Y.; Chang, Y.-W.; Marculescu, D.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design70
1942011TSV-aware analytical placement for 3D IC designs.Hsu, Meng-Kai; Chang, Yao-Wen; Balabanov, Valeriy; YAO-WEN CHANG Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011770
1952011Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011YAO-WEN CHANG 00
1962011Routability-driven analytical placement for mixed-size circuit designsHsu, M.-K.; Chou, S.; Lin, T.-H.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design630
1972011TSV-aware analytical placement for 3D IC designsHsu, M.-K.; Chang, Y.-W.; Balabanov, V.; YAO-WEN CHANG Design Automation Conference77
1982011Thermal-driven analog placement considering device matchingLin, M.P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2620
1992011Proceedings of the International Symposium on Physical Design: ForewordChang, Y.-W.; Hu, J.; YAO-WEN CHANG International Symposium on Physical Design0
2002011Timing ECO optimization via B?zier curve smoothing and fixability identificationChang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design20
2012011Cross-contamination aware design methodology for pin-constrained digital microfluidic biochipsLin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4533
2022011Escape routing for staggered-pin-array PCBsHo, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design110
2032011Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designsChuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems43
2042011Hierarchical placement with layout constraintsLin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG Analog Layout Synthesis: A Survey of Topological Approaches30
2052011A SAT-based routing algorithm for cross-referencing biochips.Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; YAO-WEN CHANG ; CHIA-LIN YANG 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011100
2062011Simultaneous functional and timing ECO.Chang, Hua-Yu; Jiang, Iris Hui-Ru; HUI-RU JIANG ; YAO-WEN CHANG Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011170
2072010Effect of Broken Symmetry on the First Hyperpolarizability of a Centrosymmetric Molecule with an Application to Furan-Containing [2.2]CyclophandieneChang, Yao-Wen ; BIH-YAW JIN Journal of the Chinese Chemical Society11
2082010TRECO: Dynamic Technology Remapping for Timing Engineering Change OrdersKuan-Hsien Ho; Jie-Hong R. Jiang; Yao-Wen Chang; YAO-WEN CHANG ; JIE-HONG JIANG Asia and South Pacific Design Automation Conference (ASP-DAC'10)149
2092010ECO timing optimization using spare cells and technology remappingHo, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1915
2102010Native-conflict-aware wire perturbation for double patterning technologyChen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design230
2112010Pulsed-latch aware placement for timing-integrity optimizationChuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference200
2122010Predictive formulae for OPC with applications to lithography-friendly routingChen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems139
2132010Recent research development in flip-chip routing.Lee, Hsu-Chieh; Chang, Yao-Wen; Lee, Po-Wei; YAO-WEN CHANG 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010160
2142010Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010YAO-WEN CHANG 00
2152010Compositional dependence of phase formation mechanisms at the interface between titanium and calcia-stabilized zirconia at 1550°CChang, Y.-W.; Lin, C.-C.; YAO-WEN CHANG Journal of the American Ceramic Society2923
2162010Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications.Tang, Jaw-Luen; Chang, Yao-Wen; YAO-WEN CHANG EURASIP J. Wireless Comm. and Networking30
2172010Fast timing-model independent buffered clock-tree synthesisShih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference230
2182010Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimizationShih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC240
2192010Unified analytical global placement for large-scale mixed-size circuit designsHsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design80
2202010Density gradient minimization with coupling-constrained dummy fill for CMP controlChen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design200
2212010ILP-based pin-count aware design methodology for microfluidic biochipsLin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2722
2222010Cross-contamination aware design methodology for pin-constrained digital microfluidic biochipsLin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference250
2232010Design-hierarchy aware mixed-size placement for routability optimizationChuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design260
2242010Multilayer global routing with via and wire capacity considerationsHsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1716
2252010High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving treesShiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design230
2262010Area-I/O flip-chip routing for chip-package co-design considering signal skewsFang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2321
2272010Template-mask design methodology for double patterning technologyHsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design20
2282010Redundant-wires-aware ECO timing and mask cost optimizationFang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design150
2292010Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesisFalkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC550
2302010Efficient provably good OPC modeling and its applications to interconnect optimization.Huang, Shih-Lun; Lin, Chung-Wei; YAO-WEN CHANG ; CHUNG-WEI LIN 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings20
2312009A novel hot-electron programming method in a buried diffusion bit-line SONOS memory by utilizing nonequilibrium charge transportWang, T.; Tang, C.-J.; Li, C.-W.; Lee, C.-H.; Ou, T.-F.; Chang, Y.-W.; Tsai, W.-J.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG IEEE Electron Device Letters00
2322009Flip-chip routing with unified area-I/O pad assignments for package-board co-design.Fang, Jia-Wei; Wong, Martin D. F.; YAO-WEN CHANG Proceedings - Design Automation Conference400
2332009Simultaneous layout migration and decomposition for double patterning technology.Hsu, Chin-Hsiung; Chang, Yao-Wen; Nassif, Sani R.; YAO-WEN CHANG 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009260
2342009Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs.Chuang, Yi-Lin; Lee, Po-Wei; Chang, Yao-Wen; YAO-WEN CHANG 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 200940
2352009Thermal-driven analog placement considering device matching.Lin, Mark Po-Hung; Zhang, Hongbo; Wong, Martin D. F.; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009260
2362009BIST design optimization for large-scale embedded memory cores.Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; CHIEN-MO LI ; YAO-WEN CHANG 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 200970
2372009ILP-based pin-count aware design methodology for microfluidic biochips.Lin, Cliff Chiung-Yu; YAO-WEN CHANG Proceedings - Design Automation Conference270
2382009Electronic Design AutomationWang, L.-T.; Chang, Y.-W.; Cheng, K.-T.; YAO-WEN CHANG Electronic Design Automation1280
2392009A novel wire-density-driven full-chip routing system for cmp variation controlChen, H.-Y.; Chou, S.-J.; Wang, S.-L.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2321
2402009High-performance global routing with fast overflow reductionQien, H.-Y.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC620
2412009Essential issues in analytical placement algorithmsChang, Y.-W.; Jiang, Z.-W.; Chen, T.-C.; YAO-WEN CHANG IPSJ Transactions on System LSI Design Methodology340
2422009Thermal-driven analog placement considering device matchingLin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference26
2432009Simultaneous layout migration and decomposition for double patterning technologyHsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design26
2442009FloorplanningChen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG Electronic Design Automation50
2452009An integer-linear-programming-based routing algorithm for flip-chip designsFang, J.-W.; Hsu, C.-H.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4538
2462009Global and Detailed RoutingChen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG Electronic Design Automation240
2472009Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designsLee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design100
2482009Voltage-island partitioning and floorplanning under timing constraintsLee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1411
2492009Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designsChuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design4
2502009An efficient pre-assignment routing algorithm for flip-chip designsLee, P.-W.; Lin, C.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design15
2512009Analog placement based on symmetry-island formulationLin, P.-H.; Lin, S.-C.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems7264
2522009Routing for manufacturability and reliabilityChen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Circuits and Systems Magazine88
2532009IntroductionStroud, C.E.; Wang, L.T.; Chang, Y.-W.; YAO-WEN CHANG Electronic Design Automation20
2542009A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochipsYuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems25
2552009Voltage-Island partitioning and floorplanning under timing constraintsLee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems111
2562009BIST design optimization for large-scale embedded memory coresChien, T.-F.; Chao, W.-C.; Li, C.-M.; Chang, Y.-W.; Liao, K.-Y.; Chang, M.-T.; Tsai, M.-H.; Tseng, C.-M.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design7
2572009Spare-cell-aware multilevel analytical placementJiang, Z.-W.; Hsu, M.-K.; Chao, K.-Y.; YAO-WEN CHANG Design Automation Conference7
2582009T-trees: A tree-based representation for temporal and three-dimensional floorplanningYuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG ACM Transactions on Design Automation of Electronic Systems63
2592009Analog layout synthesis - Recent advances in topological approachesGraeb, H.; Balasa, F.; Castro-Lopez, R.; Chang, Y.-W.; Fern; ez, F.V.; Lin, P.-H.; Strasser, M.; YAO-WEN CHANG Design, Automation and Test in Europe, DATE34
2602009An efficient pre-assignment routing algorithm for flip-chip designs.Lee, Po-Wei; Lin, Chung-Wei; Chang, Yao-Wen; Shen, Chin-Fang; CHUNG-WEI LIN ; YAO-WEN CHANG 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009150
2612008奈米IC設計之前瞻電子設計自動化技術-子計畫五:在奈米製程下考量可製造性和可靠度之實體設計 (新制多年期第1年)張耀文 
2622008奈米IC設計之前瞻電子設計自動化技術-總計畫 (新制多年期第1年)張耀文 
2632008超大型奈米積體電路無格線式全晶片繞線系統之研究(3/3)張耀文 
2642008兆級晶片系統前瞻技術研究-子計畫六:兆級晶片系統實體整合之研究(2/3)張耀文 
2652008Packing Floorplan Representations.Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG Handbook of Algorithms for Physical Design Automation.
2662008MP-trees: A packing-based macro placement algorithm for modern mixed-size designsChen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, T.-Y.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems3027
2672008A New Multilevel Framework for Large-Scale Interconnect-Driven FloorplanningChen, Tung-Chieh; Chang, Yao-Wen ; Lin, Shyh-ChangIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems24
2682008Area-I/O flip-chip routing for chip-package co-designFang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design450
2692008A progressive-ILP based routing algorithm for cross-referencing biochipsYuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG Design Automation Conference690
2702008Effect of yttria on interfacial reactions between titanium melt and hot-pressed yttria/zirconia composites at 1700°cLin, C.-C.; Chang, Y.-W.; Lin, K.-L.; YAO-WEN CHANG Journal of the American Ceramic Society2416
2712008Routing for chip-package-board co-design considering differential pairsFang, J.-W.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design220
2722008Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs.Jiang, Zhe-Wei; Su, Bor-Yiing; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 200800
2732008Predictive formulae for OPC with applications to lithography-friendly routing.Chen, Tai-Chen; Liao, Guang-Wan; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 200800
2742008NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraintsChen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems236200
2752008BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochipsYuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems7755
2762008Predictive formulae for OPC with applications to lithography-friendly routingChen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference200
2772008Sensitivity-based multiple-Vt cell swapping for leakage power reductionLee, W.-P.; Liu, H.-Y.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT10
2782008Multilayer obstacle-avoiding rectilinear steiner tree construction based on spanning graphsLin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Lee, M.-X.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1821
2792008Metal-density driven placement for CMP variation and routabilityChen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design60
2802008Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designsJiang, Z.-W.; Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference370
2812008Multi-layer global routing considering via and wire capacitiesHsu, C.-H.; Chen, H.-Y.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design280
2822008Effective wire models for X-architecture placementChen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems11
2832008Metal-density-driven placement for CMP variation and routabilityChen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1313
2842008Constraint graph-based macro placement for modern mixed-size circuit designsChen, H.-C.; Chuang, Y.-L.; Chang, Y.-W.; Chang, Y.-C.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design260
2852008Effective Wire Models for X-Architecture PlacementChen, Tung-Chieh; Chuang, Yi-Lin; Chang, Yao-Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1
2862008A new multilevel framework for large-scale interconnect-driven floorplanningChen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2825
2872008Full-chip routing considering double-via insertionChen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems6146
2882008An optimal network-flow-based simultaneous diode and jumper insertion algorithm for antenna fixingJiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems85
2892008Full-Chip Routing Considering Double-Via InsertionChen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, B.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems46
2902008An efficient graph-based algorithm for ESD current path analysisLiu, Chih-Hung; Liu, Hung-Yi; Lin, Chung-Wei; Chou, Szu-Jui; Chang, Yao-Wen; Kuo, Sy-Yen; Yuan, Shih-Yi; CHUNG-WEI LIN ; CHIH-HUNG LIU ; YAO-WEN CHANG ; SY-YEN KUO Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems74
2912008A progressive-ILP based routing algorithm for cross-referencing biochips.Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 200800
2922008Obstacle-avoiding rectilinear steiner tree construction based on spanning graphsChen, S.-Y.; Li, C.-F.; CHIA-LIN YANG ; CHUNG-WEI LIN ; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems5346
2932007兆級晶片系統前瞻技術研究-子計畫六:兆級晶片系統實體整合之研究(3/3)張耀文 
2942007車用聚碳酸酯風擋及車窗之設計及熱成形技術研究鄭榮和 ; 張耀文 ; 張智凱; 李聚儒
2952007Full-Chip Nanometer Routing Techniques.Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; YAO-WEN CHANG 
2962007NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs.Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG Modern Circuit Placement, Best Practices and Results
2972007Multilevel full-chip gridless routing with applications to optical-proximity correctionChen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1913
2982007Multilevel full-chip routing with testability and yield enhancementLi, K.S.-M.; Chang, Y.-W.; Lee, C.-L.; Su, C.; Chen, J.E.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems105
2992007Statistical circuit optimization considering device andinterconnect process variationsLin, I.-J.; Ling, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG International Workshop on System Level Interconnect Prediction, SLIP40
3002007An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007570
3012007X-route: An x-architecture full-chip multilevel routerChang, C.-F.; Chang, Y.-W.; YAO-WEN CHANG 20th Anniversary IEEE International SOC Conference40
30220073D Video Applications and Intelligent Video Surveillance Camera and its VLSI DesignChien, hao-Yi; Shih, Chi-Sheng ; Ku, Mong-Kai; Yang, Chia-Lin ; Chang, Yao-Wen ; Kuo, Tei-Wei ; Chen, Liang-Gee 2007 IEEE International Conference on Multimedia and Expo, ICME 20070
3032007Novel wire density driven full-chip routing for CMP variation controlChen, H.-Y.; Chou, S.-J.; Wang, S.-L.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD160
3042007A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages.Liu, Hung-Yi; Lee, Wan-Ping; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 200700
3052007An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.Fang, Jia-Wei; Hsu, Chin-Hsiung; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 200700
3062007MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.Chen, Tung-Chieh; Yuh, Ping-Hung; Chang, Yao-Wen; Huang, Fwu-Juh; Liu, Denny; YAO-WEN CHANG Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 200700
3072007An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstaclesSu, B.-Y.; Hu, J.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems52
3082007Multilevel Full-Chip Routing With Testability and Yield EnhancementLi, Katherine Shu-Min; Chang, Yao-Wen ; Lee, Chung-Len; Su, Chauchin; Chen, Jwu E.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems5
3092007MB^*-Tree: A Multilevel Floorplanner for Large-Scale Building-Module DesignLee, Hsun-Cheng; Chang, Yao-Wen ; Yang, Hannah HonghuaIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 
3102007Thermal-driven interconnect optimization by simultaneous gate and wire sizingLin, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 200600
3112007Challenges and solutions in modern VLSI placementJiang, Z.-W.; Chen, H.-.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG 2007 International Symposium on VLSI Design, Automation and Test60
3122007Power/ground network and floorplan cosynthesis for fast design convergenceLiu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1913
3132007A statistical approach to the timing-yield optimization of pipeline circuitsHsu, C.-H.; Chou, S.-J.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG Lecture Notes in Computer Science0
31420073D video applications and intelligent video surveillance camera and its VLSI designChien, S.-Y.; Shih, C.-S.; Ku, M.-K.; Yang, C.-L.; Chang, Y.-W.; Kuo, T.-W.; Chen, L.-G.; YAO-WEN CHANG 2007 IEEE International Conference on Multimedia and Expo, ICME 20070
3152007A Network-Flow-Based RDL Routing Algorithm for Flip-Chip DesignFang, Jia-Wei; Lin, I-Jye; Chang, Yao-Wen ; Wang, Jyh-HerngIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 
3162007An integer linear programming based routing algorithm for flip-chip designFang, J.-W.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference510
3172007ECO timing optimization using spare cellsChen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design430
3182007An optimal jumper-insertion algorithm for antenna avoidance/fixingSu, B.-Y.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems85
3192007MP-trees: A packing-based macro placement algorithm for mixed-size designsChen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG Design Automation Conference140
3202007Temporal floorplanning using the three-dimensional transitive closure subGraphYuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG ACM Transactions on Design Automation of Electronic Systems2117
3212007MB*-tree: A multilevel floorplanner for large-scale building-module designLee, H.-C.; Chang, Y.-W.; Yang, H.H.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems42
3222007X-architecture placement based on effective wire modelsChen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design10
3232007A new interference phenomenon in sub-60nm nitride-based flash memoryChang, Y.W.; YAO-WEN CHANG et al. 22nd IEEE Non-Volatile Semiconductor Memory Workshop50
3242007A network-flow-based RDL routing algorithmz for flip-chip designFang, J.-W.; Lin, I.-J.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems5944
3252007An efficient algorithm for statistical circuit optimization using Lagrangian relaxationLin, I.-J.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design20
3262007Power/Ground Network and Floorplan Cosynthesis for Fast Design ConvergenceLiu, Chen-Wei; Chang, Yao-Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems13
3272007Efficient multi-layer obstacle-avoiding rectilinear steiner tree constructionLin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Li, M.-X.; YAO-WEN CHANG ; CHUNG-WEI LIN IEEE/ACM International Conference on Computer-Aided Design150
3282007Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity CorrectionChen, Tai-Chen; Chang, Yao-Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems13
3292007An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/FixingSu, Bor-Yiing; Su, Bor-Yiing; Chang, Yao-Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems5
33020073D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; CHIA-LIN YANG ; CHI-SHENG SHIH ; TEI-WEI KUO ; LIANG-GEE CHEN ; YAO-WEN CHANG ; SHAO-YI CHIEN Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China00
3312007Efficient obstacle-avoiding rectilinear steiner tree construction.Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG ; CHUNG-WEI LIN Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007360
3322007Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.Lin, Chung-Wei; Tsai, Ming-Chao; Lee, Kuang-Yao; Chen, Tai-Chen; Wang, Ting-Chi; YAO-WEN CHANG ; CHUNG-WEI LIN Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007140
3332006Inductance extraction for general interconnect structuresLai, Chun-Ying; Jeng, Shyh-Kang ; Chang, Yao-Wen ; Tsai, Chia-ChunInternational Symposium on Circuits and Systems, 2006. ISCAS '0600
3342006Modern Floorplanning Based on B?-Tree and Fast Simulated AnnealingChen, Tung-Chieh; Chang, Yao-Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 
3352006A novel framework for multilevel full-chip gridless routingChen, Tai-Chen; Chang, Yao-Wen ; Lin, Shyh-ChangAsia and South Pacific Conference on Design Automation, 2006.00
3362006An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstaclesSu, B.-Y.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG International Symposium on Physical Design7
3372006Multilevel routing with jumper insertion for antenna avoidanceHo, T.-Y.; YAO-WEN CHANG ; SAO-JIE CHEN Integration, the VLSI Journal52
3382006An optimal simultaneous diode/jumper insertion algorithm for antenna fixing.Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 200600
3392006An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.Su, Bor-Yiing; Chang, Yao-Wen; Hu, Jiang; YAO-WEN CHANG Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 200670
3402006Floorplan and power/ground network co-synthesis for fast design convergence.Liu, Chen-Wei; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006220
3412006NTUplace2: a hybrid placer using partitioning and analytical techniques.Jiang, Zhe-Wei; Chen, Tung-Chieh; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 200600
3422006Voltage island aware floorplanning for power and timing optimization.Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 200600
3432006A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 200600
3442006IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faultsLi, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC0
3452006Current path analysis for electrostatic discharge protectionLiu, H.-Y.; Lin, C.-W.; Chou, S.-J.; Tu, W.-T.; Liu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG ; SY-YEN KUO ; CHUNG-WEI LIN ; CHIH-HUNG LIU IEEE/ACM International Conference on Computer-Aided Design80
3462006An optimal simultaneous diode/jumper insertion algorithm for antenna fixingJiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design40
3472006A high-quality mixed-size analytical placer considering preplaced blocks and density constraintsChen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design620
3482006Modern floorplanning based on B*-tree and fast simulated annealingChen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems11779
3492006Placement of digital microfluidic biochips using the T-tree formuationYuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen 43rd annual Design Automation Conference 
3502006Floorplan and power/ground network co-synthesis for fast design convergenceLiu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design22
3512006Charge-based capacitance measurement for bias-dependent capacitanceChang, Y.-W.; Chang, H.-W.; Lu, T.-C.; King, Y.-C.; Ting, W.; Ku, Y.-H.J.; Lu, C.-Y.; YAO-WEN CHANG IEEE Electron Device Letters4436
3522006A novel framework for multilevel full-chip gridless routingChen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC14
3532006Novel full-chip gridless routing considering double-via insertionChen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG Design Automation Conference310
3542006RLC coupling-aware simulation and on-chip bus encoding for delay reductionTu, S.-W.; Jou, J.-Y.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems3723
3552006Simultaneous block and I/O buffer floorplanning for flip-chip designPeng, C.-Y.; Chao, W.-C.; Wang, J.-H.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC14
3562006Voltage Island aware floorplanning for power and timing optimizationLee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design740
3572006IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faultsLi, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems119
3582006NTUplace2: A hybrid placer using partitioning and analytical techniquesJiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design24
3592006Inductance extraction for general interconnect structuresLai, C.-Y.; Jeng, S.-K.; Chang, Y.-W.; Tsai, C.-C.; YAO-WEN CHANG IEEE International Symposium on Circuits and Systems0
3602006Physical design for System-On-a-ChipChang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG Essential Issues in SOC Design: Designing Complex Systems-on-Chip10
3612006Novel Full-Chip Gridless Routing Considering Double-Via InsertionChen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, Brian
3622006Placement of digital microfluidic biochips using the t-tree formulationYuh, P.-H.; Yang, C.-L.; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings - Design Automation Conference440
3632006Reliable crosstalk-driven interconnect optimization.Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG ACM Trans. Design Autom. Electr. Syst.02
3642006Current path analysis for electrostatic discharge protection.Liu, Hung-Yi; Lin, Chung-Wei; Chou, Szu-Jui; Tu, Wei-Ting; Liu, Chih-Hung; Chang, Yao-Wen; CHUNG-WEI LIN ; SY-YEN KUO ; YAO-WEN CHANG 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 200600
3652005超大型?米積體電?無格線式全晶片繞線系統 (1/3) Gridless Full-Chip Routing for Very-Large Scale Nanometer ICs張耀文 
3662005Crosstalk- and Performance-Driven Multilevel Full-Chip RoutingHo, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie ; Lee, Der-TsaiIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 
3672005SoC test scheduling using the B*-tree based floorplanning techniqueWuu, Jen-Yi; Chen, Tung-Chieh; Chang, Yao-Wen Asia and South Pacific Design Automation Conference, ASP-DAC 200500
3682005TCG: A transitive closure graph based representation for general floorplansLin, Jai-Ming; Chang, Yao-Wen IEEE Transactions on 
3692005SoC test scheduling using the B*-tree based floorplanning techniqueWuu, J.-Y.; Chen, T.-C.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC15
3702005Multilevel full-chip routing for the X-based architecture.SAO-JIE CHEN ; Chang, Chen-Feng; YAO-WEN CHANG ; Ho T.-YProceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005390
3712005Multilevel full-chip routing with testability and yield enhancementLi, K.S.-M.; Lee, C.-L.; Chang, Y.-W.; Su, C.; Chen, J.-E.; YAO-WEN CHANG International Workshop on System Level Interconnect Prediction, SLIP2
3722005NTUplace: A ratio partitioning based placement algorithm for large-scale mixed-size designsChen, T.-C.; Hsu, T.-C.; Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design50
3732005An exact jumper insertion algorithm for antenna effect avoidance/fixing.Su, Bor-Yiing; YAO-WEN CHANG Proceedings - Design Automation Conference100
3742005Multilevel full-chip routing with testability and yield enhancement.Li, Katherine Shu-Min; Lee, Chung-Len; Chang, Yao-Wen; Su, Chauchin; Chen, Jwu E.; YAO-WEN CHANG The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings20
3752005Modern floorplanning based on fast simulated annealing.Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005590
3762005Multilevel full-chip gridless routing considering optical proximity correction.Chen, Tai-Chen; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005200
3772005NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.Chen, Tung-Chieh; Hsu, Tien-Chang; Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 200500
3782005TCG: A transitive closure graph-based representation for general floorplansLin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Very Large Scale Integration (VLSI) Systems4837
3792005Multilevel full-chip routing for the X-based architectureHo, Tsung-Yi; Chang, Chen-Feng; Chang, Yao-Wen ; Chen, Sao-Jie Design Automation Conference 
3802005Delay modeling for buffered RLY/RLC treesWang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test140
3812005Crosstalk- and performance-driven multilevel full-chip routingHo, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.-T.; YAO-WEN CHANG ; SAO-JIE CHEN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4833
3822005Multilevel routing with antenna avoidanceHo, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-JieBulletin of the College of Engineering 
3832005Multilevel full-chip gridless routing considering optical proximity correctionChen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC20
3842005IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designsChen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design430
3852005多媒體通訊系統中可重組化運算技術之研究─子計畫五:可重組化系統之實體設計(3/3)張耀文 
3862005Modern floorplanning based on fast simulated annealingChen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG International Symposium on Physical Design59
3872005Placement with symmetry constraints for analog layout design using TCG-SLin, J.-M.; Wu, G.-M.; Chuang, J.-H.; YAO-WEN CHANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC43
3882005Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reductionTu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE International Symposium on Circuits and Systems60
3892005Reconfigurable platform for content science researchLIANG-GEE CHEN ; TEI-WEI KUO ; YAO-WEN CHANG ; SHAO-YI CHIEN ; CHIA-LIN YANG ; CHI-SHENG SHIH ; Ku, Mong-Kai11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications00
3902005A routing algorithm for flip-chip designFang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Wang, J.-H.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design430
3912005Joint exploration of architectural and physical design spaces with thermal consideration.Wu, Yen-Wei; Yang, Chia-Lin; Yuh, Ping-Hung; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005180
3922004Temporal floorplanning using the T-tree formulationYuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004.
3932004Physical Design for Reconfigurable Computing System張耀文 
3942004Area, Delay, Power, and Noise Optimization for Transmission Lines張耀文 
3952004MR: A New Framework for Multilevel Full-Chip RoutingYAO-WEN CHANG ; Lin, Shih-PingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4034
3962004提升鈦合金超塑性成形及擴散接合技術研究(二)鄭榮和 ; 張耀文 ; 曾炳瑋
3972004Layout techniques for on-chip interconnect inductance reductionTu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC1
3982004Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.Cheng, Yi-Hui; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 200400
3992004Multilevel routing with jumper insertion for antenna avoidanceHo, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG IEEE International SOC Conference1
4002004TCG-S: Orthogonal Coupling of P^*-Admissible Representations for General FloorplansLin, Jai-Ming; Chang, Yao-Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 
4012004Temporal floorplanning using the T-tree formulationYuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design62
4022004Temporal Floorplanning Using 3D-subTCGYuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen ; Chen, Hsin-LungAsia and South Pacific Design Automation Conference, ASP-DAC 
4032004Timing modeling and optimization under the transmission line modelChen, Tai-Chen; Pan, Song-Ra; Chang, Yao-Wen IEEE Transactions on3227
4042004Layout techniques for on-chip interconnect inductance reduction.Tu, Shang-Wei; Jou, Jing-Yang; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 200400
4052004Placement with alignment and performance constraints using the B*-tree representationWu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG IEEE International Conference on Computer Design: VLSI in Computers and Processors150
4062004Integrating buffer planning with floorplanning for simultaneous multi-objective optimizationCheng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC8
4072004Multilevel routing with antenna avoidance.Ho, Tsung-Yi; SAO-JIE CHEN ; YAO-WEN CHANG Proceedings of the International Symposium on Physical Design360
4082004Efficient power/ground network analysis for power integrity-driven design methodology.Wu, Su-Wei; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004210
4092004TCG-S: Orthogonal coupling of P*-admissible representations for general floorplansLin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4423
4102004Efficient power/ground network analysis for power integrity-driven design methodologyWu, S.-W.; Chang, Y.-W.; YAO-WEN CHANG Design Automation Conference21
4112004Universal switch blocks for three-dimensional FPGA designWu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG IEE Proceedings: Circuits, Devices and Systems97
4122004RLC effects on worst-case switching pattern for on-chip busesTu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG IEEE International Symposium on Circuits and Systems10
4132004A reusable methodology for non-slicing floorplanningHsu, J.-M.; Chang, Y.-W.; YAO-WEN CHANG IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS1
4142004Temporal floorplanning using 3D-subTCGYuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC42
4152004Multilevel routing with jumper insertion for antenna avoidanceHo, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie IEEE International SOC Conference00
4162004Simultaneous Floorplan and Buffer-Block OptimizationHUI-RU JIANG ; YAO-WEN CHANG ; Jou, Jing-Yang; Chao, Kai-YuanIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems102
4172004A clustering- and probability-based approach for time-multiplexed FPGA partitioningWu, Guang-Ming; Chao, Mango Chia-Tso; YAO-WEN CHANG Integration10
4182004Temporal floorplanning using the T-tree formulation.Yuh, Ping-Hung; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 200400
4192004Temporal floorplanning using 3D-subTCG.Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 200400
4202003Physical Design for Reconfigurable Computing System張耀文 
4212003Area, Delay, Power , and Noise Optimization for Transmission Lines張耀文 
4222003A fast crosstalk- and performance-driven multilevel routing systemHo, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie ; Lee, D.T.IEEE/ACM International Conference on Computer-Aided Design00
4232003Noise-aware buffer planning for interconnect-driven floorplanningLi, S.-M.; Cherng, Y.-H.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC60
4242003Analysis of FPGA/FPIC switch modulesZhu, K.; Wu, G.-M.; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG ACM Transactions on Design Automation of Electronic Systems23
4252003Simultaneous floorplanning and buffer block planningHui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC110
4262003Graph matching-based algorithms for array-based FPGA segmentation design and routing.Lin, Jai-Ming; Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 200300
4272003Multilevel floorplanning/placement for large-scale modules using B*-trees.Lee, Hsun-Cheng; Chang, Yao-Wen; Hsu, Jer-Ming; Yang, Hannah Honghua; YAO-WEN CHANG Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 200300
4282003Inductance Modeling for On-Chip InterconnectsTu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen ; Chen, Tai-Chen; Jou, Jing-YangAnalog Integrated Circuits and Signal Processing54
4292003Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing schemeLin, Jai-Ming; YAO-WEN CHANG ; Lin, Shih-PingIEEE Transactions on Very Large Scale Integration (VLSI) Systems4236
4302003Rectilinear block placement using B*-treesWu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG ACM Transactions on Design Automation of Electronic Systems2521
4312003Multilevel floorplanning/placement for large-scale modules using B*-treesLee, H.-C.; Chang, Y.-W.; Hsu, J.-M.; Yang, H.H.; YAO-WEN CHANG Design Automation Conference28
4322003A Fast Crosstalk- and Performance-Driven Multilevel Routing SystemHo, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design46
4332003Graph matching-based algorithms for array-based FPGA segmentation design and routingLin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG Asia and South Pacific Design Automation Conference, ASP-DAC20
4342003Simultaneous floorplanning and buffer block planning.Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 200300
4352002Performance Optimization Under the Transmission Line Model張耀文 
4362002Arbitrarily shaped rectilinear module placement using the transitive closure graph representationLin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Very Large Scale Integration (VLSI) Systems89
4372002A novel framework for multilevel routing considering routability and performanceLin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design550
4382002Inductance modeling for on-chip interconnectsTu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG Proceedings - IEEE International Symposium on Circuits and Systems20
4392002TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 200200
4402002Module placement with boundary constraints using B*-treesLin, J.-M.; Yi, H.-E.; YAO-WEN CHANG IEE Proceedings: Circuits, Devices and Systems1811
4412002Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian RelaxationLEE, YU-MIN; CHEN, CHARLIE CHUNG-PING; YAO-WEN CHANG ; CHUNG-PING CHEN VLSI Design42
4422002Comment on "generic universal switch blocks"Fan, H.; Wu, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computers66
4432002Arbitrary convex and concave rectilinear module packing using TCGLin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG Design, Automation and Test in Europe, DATE60
4442002Comment on "Generic universal switch blocks"Fan, Hongbing; Wu, Yu-Liang; Chang, Yao-Wen IEEE Transactions on Computers 
4452002Inductance modeling for on-chip interconnectsTu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG IEEE International Symposium on Circuits and Systems2
4462002Performance-driven placement for dynamically reconfigurable FPGAsWu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG ACM Transactions on Design Automation of Electronic Systems00
4472002Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 200210
4482001Performance optimization by wire and buffer sizing under the transmission line modelChen, Tai-Chen; Pan, Song-Ra; YAO-WEN CHANG Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors30
4492001An algorithm for dynamically reconfigurable FPGA placementWu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors60
4502001Generic ILP-based approaches for dynamically reconfigurable FPGA partitioningWu, G.-M.; Lin, J.-M.; Chao, M.C.-T.; Chang, Y.-W.; YAO-WEN CHANG Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors00
4512001TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 200100
4522001Matching-Based Algorithm for FPGA Channel Segmentation DesignYAO-WEN CHANG ; Lin, Jai-Ming; Wong, M. D. F.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems66
4532001Generic ILP-based approaches for time-multiplexed FPGA partitioningWu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems3022
4542001Performance optimization by wire and buffer sizing under the transmission line modelChen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG IEEE International Conference on Computer Design: VLSI in Computers and Processors3
4552000Timing-driven routing for symmetrical array-based FPGAsZhu, K.; Wong, D.F.; YAO-WEN CHANG ACM Transactions on Design Automation of Electronic Systems2320
4562000Crosstalkdriven interconnect optimization by simultaneous gate and wire sizingJiang, I.H.R.; Chang, Y.W.; Jou, J.Y.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10
4572000Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 200000
4582000B * -trees: A new representation for non-slicing floorplansChang, Y.-C.; Chang, Y.-W.; Wu, G.-M.; Wu, S.-W.; YAO-WEN CHANG Proceedings-Design Automation Conference4660
4592000Rectilinear Block Placement Using B*-Trees.Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 200000
4602000Rectilinear block placement using B*-treesWu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG IEEE International Conference on Computer Design: VLSI in Computers and Processors9
4612000An architecture-driven metric for simultaneous placement and global routing for FPGAs.Chang, Yao-Wen; Chang, Yu-Tsang; YAO-WEN CHANG Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000.120
4622000B*-Trees: a new representation for non-slicing floorplans.Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000.00
4632000Timing-driven routing for symmetrical-array-based FPGAsCHANG, YAO-WEN ; ZHU, KAI; WONG, D. F.ACM Transactions on Design Automation of Electronic Systems 
4642000Generic universal switch blocksShyu, M.; Wu, G.-M.; Chang, Y.-D.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computers3228
4652000Optimal reliable crosstalk-driven interconnect optimizationJiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG International Symposium on Physical Design7
4662000B<sup>*</sup>-trees: a new representation for non-slicing floorplansChang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG Design Automation Conference466
4672000Architecture-driven metric for simultaneous placement and global routing for FPGAsChang, Yao-Wen; Chang, Yu-Tsang; YAO-WEN CHANG Design Automation Conference12
4682000Crosstalk-constrained performance optimization by using wire sizing and perturbationPan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG IEEE International Conference on Computer Design: VLSI in Computers and Processors13
4692000Optimal reliable crosstalk-driven interconnect optimization.Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 200070
4702000Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG IEEE Trans. on CAD of Integrated Circuits and Systems4940
4711999Generic universal switch blocksShyu, Michael; Chang, Yu-Dong; Wu, Guang-Ming; Chang, Yao-Wen; YAO-WEN CHANG IEEE International Conference on Computer Design: VLSI in Computers and Processors10
4721999Universal Switch Blocks for Three-Dimensional FPGA Design.Wu, Guang-Ming; Shyu, Michael; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 199900
4731999Clustering- and probability-based approach for time-multiplexed FPGA partitioningChao, Mango Chia-Tso; Wu, Guang-Ming; Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design17
4741999Quasi-universal switch matrices for FPD designWu, G.-M.; Chang, Y.-W.; YAO-WEN CHANG IEEE Transactions on Computers63
4751999A clustering- and probability-based approach for time-multiplexed FPGA partitioning.Chao, Mango Chia-Tso; Wu, Guang-Ming; Jiang, Iris Hui-Ru; HUI-RU JIANG ; YAO-WEN CHANG Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 199900
4761999Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.Jiang, Iris Hui-Ru; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999.90
4771998Timing-driven routing for symmetrical-array-based FPGAs.Zhu, Kai; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA100
4781998Graph matching-based algorithms for FPGA segmentation design.Lin, Jai-Ming; Wong, D. F.; YAO-WEN CHANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers70
4791998Switch-matrix architecture and routing for FPDsWu, Guang-Min; YAO-WEN CHANG International Symposium on Physical Design2
4801998Maximally routable switch matrices for FPD designWu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG IEEE International Symposium on Circuits and Systems0
4811998Timing-driven routing for symmetrical-array-based FPGAsZhu, Kai; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG IEEE International Conference on Computer Design: VLSI in Computers and Processors10
4821997Algorithms for an FPGA switch module routing problem with application to global routingThakur, S.; Chang, Y.-W.; Wong, D.F.; Muthukrishnan, S.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems137
4831997Graph-theoretic sufficient condition for FPGA/FPIC switch-module routabilityWong, D.F.; Wong, C.K.; YAO-WEN CHANG IEEE International Symposium on Circuits and Systems0
4841996A velocity-overshoot capacitance model for 0.1 μm MOS transistorsKuo, J.B.; Chang, Y.W.; Lai, C.S.; YAO-WEN CHANG Solid-State Electronics44
4851996An analytical velocity overshoot model for 0.1 μm N-channel metal-oxide-silicon devices considering energy transportJAMES-B KUO ; YAO-WEN CHANG ; Chen Y.-G.Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers10
4861996Universal Switch-Module Design for Symmetric-Array-Based FPGAs.Wong, D. F.; Wong, C. K.; YAO-WEN CHANG Proceedings of the 1996 ACM 4th International Symposium on Field-Programmable Gate Arrays, FPGA 199600
4871996Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation.Chen, Chung-Ping; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996.240
4881996On a new timing-driven routing tree problemWong, D.F.; Zhu, Kai; Wong, C.K.; YAO-WEN CHANG Proceedings - IEEE International Symposium on Circuits and Systems2
4891996Universal switch-module design for symmetric-array-based FPGAsWong, D.F.; Wong, C.K.; YAO-WEN CHANG ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA200
4901996Universal switch modules for fpga designWong, D.F.; Wong, C.K.; YAO-WEN CHANG ACM Transactions on Design Automation of Electronic Systems103
4911996Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxationChen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG Design Automation Conference24
4921995Design and analysis of FPGA/FPIC switch modules.Wong, D. F.; Wong, C. K.; YAO-WEN CHANG Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors50
4931995FPGA global routing based on a new congestion metricWong, D.F.; Wong, C.K.; YAO-WEN CHANG IEEE International Conference on Computer Design: VLSI in Computers and Processors13
4941994A new global routing algorithm for FPGAs.Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D. F.; YAO-WEN CHANG Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 199400
4951994New global routing algorithm for FPGAsChang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems13
4961993Switch module design with application to two-dimensional segmentation designZhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG 15
4971993Switch module design with application to two-dimensional segmentation design.Zhu, Kai; Wong, D. F.; Chang, Yao-Wen; YAO-WEN CHANG Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 199300