第 1 到 50 筆結果,共 50 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2009 | Adaptive Channel-Shortened Interpolated Echo and NEXT Canceller Designs Applied to 10GBASE-T Ethernet System | Chen, Yen-Liang; Zhan, Cheng-Zhou; Jheng, Ting-Jyun; Wu, An-Yeu | International Journal of Electrical Engineering | |||
2 | 2009 | Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor | Lin, Shu-Yen ; Shen, Wen-Chung; Hsu, Chan-Cheng; Wu, An-Yeu | International Journal of Electrical Engineering | |||
3 | 2009 | Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits | Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu ; Chen, Jie | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
4 | 2007 | 適用於異質無線網路環境之前瞻MoIP手持裝置SoC設計(1/3) | 吳安宇 | ||||
5 | 2006 | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time | Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
6 | 2006 | A portable all-digital pulsewidth control loop for SOC applications | Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
7 | 2005 | Polar transmitter for wireless communication system | Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai ; Jheng, Kai-Yuan; Wu, An-Yeu | 2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005 | 0 | 0 | |
8 | 2005 | A new stopping criterion for efficient early termination in turbo decoder designs | Li, Fan-Min; Wu, An-Yeu | 2005 International Symposium on Intelligent Signal Processing and Communication Systems | 0 | 0 | |
9 | 2005 | 子計畫四:可重組化通訊運算引擎的設計與實現(3/3) | 吳安宇 | ||||
10 | 2005 | Digital signal processing engine design for polar transmitter in wireless communication systems | AN-YEU(ANDY) WU ; Ko, H.-Y.; Wang, Y.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
11 | 2005 | A high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T.; Wang, W.; AN-YEU(ANDY) WU | 2005 PhD Research in Microelectronics and Electronics | |||
12 | 2005 | A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
13 | 2005 | Low cost decision feedback equalizer (DFE) design for giga-bit systems | AN-YEU(ANDY) WU ; Lin, C.-H.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
14 | 2005 | A scalable DCO design for portable ADPLL designs | AN-YEU(ANDY) WU ; Wu, C.-T.; Wang, W.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
15 | 2004 | Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel | Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | 0 | 0 | |
16 | 2004 | Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems | Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu | IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 0 | 0 | |
17 | 2004 | 適用於高速光通訊之數位基頻電路設計(I) | 吳安宇 | ||||
18 | 2004 | 用戶線路之頻域等化器技術設計與研究 | 吳安宇 | ||||
19 | 2004 | Least squares approximation-based ROM-free direct digital frequency synthesizer | Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu | International Symposium on Circuits and Systems, 2004. ISCAS '04 | |||
20 | 2004 | 1000BASE-T Gigabit Ethernet baseband DSP IC design | Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | |||
21 | 2004 | VLSI design of dual-mode Viterbi/turbo decoder for 3GPP | Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | |||
22 | 2004 | A scalable Reed-Solomon decoding processor based on unified finite-field processing element design | Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
23 | 2004 | 多媒體通訊系統中可重組化運算技術之研究─子計畫四:可重組化通訊運算引擎的設計與實現(2/3) | 吳安宇 | ||||
24 | 2004 | Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design | Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
25 | 2003 | 多媒體通訊系統中可重組化運算技術之研究─子計畫四: 可重組化通訊運算引擎之設 計與實現(1/3) | 吳安宇 | ||||
26 | 2003 | Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems | Kuo, Jen-Chih; Wen, Ching-Hua; Wu, An-Yeu | 2003 International Symposium on Circuits and Systems. ISCAS '03 | 0 | 0 | |
27 | 2003 | Angle quantization approach for lattice IIR filter implementation and its trellis de-allocation algorithm | Wu, An-Yeu ; Lee, I-Hsien; Wu, Cheng-Shing | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | 0 | 0 | |
28 | 2003 | Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-performance rotational operations | Lin, Zhi-Xiu; Wu, An-Yeu | IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003 | 0 | 0 | |
29 | 2003 | 2002 IEEE 信號系統研討會 | 吳安宇 | ||||
30 | 2003 | A Novel Echo Cancellation Algorithm and Architecture Based on Multi-Path Adaptive Interpolated FIR Filter | Wu, Cheng-Shing; Wu, An-Yeu | Journal of the Chinese Institute of Electrical Engineering | |||
31 | 2003 | Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems | AN-YEU(ANDY) WU ; Chen, P.-H.; Kai-Huang; Hsueh, N.-H.; AN-YEU(ANDY) WU | IEEE International SOC Conference, SOCC 2003 | |||
32 | 2003 | VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems | Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu | Eurasip Journal on Applied Signal Processing | 45 | 33 | |
33 | 2003 | A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm | Hsu, Huai-Yi; Wang, Sheng-Feng; Wu, An-Yeu | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology | 2 | 1 | |
34 | 2002 | A Unified View for Vector Rotational CORDIC Algorithms and Architectures Based on Angle Quantization Approach | Wu, An-Yeu ; Wu, Cheng-Shing | IEEE Transactions on Circuits and Systems Part I | |||
35 | 2002 | High-performance adaptive decision feedback equalizer based on predictive parallel branch slicer scheme | Yang, Meng-Da; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
36 | 2002 | CORDIC(COordinate Rotation Dlgital Computer) | Hu, Y.H.; 吳安宇 | ||||
37 | 2002 | 適用於高數位用戶迴路之DMT 數位IP 模組設計及實現 (II) | 吳安宇 | ||||
38 | 2002 | A new pipelined adaptive DFE architecture with improved convergence rate | Yang, Meng-Da; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
39 | 2002 | Basic Division Scheme | 吳安宇 | ||||
40 | 2002 | VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems | AN-YEU(ANDY) WU ; Hsu, H.-Y.; AN-YEU(ANDY) WU | 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 | |||
41 | 2002 | A Reduced-complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems | Chan, Tsun-Shan; Kuo, Jen-Chih; Wu, An-Yeu | EURASIP Journal on Applied Signal Processing | 3 | 2 | |
42 | 2001 | A very low-cost multi-mode Reed Solomon decoder based on Peterson-Gorenstein-Zierler algorithm | Wang, Sheng-Feng; Hsu, Huai-Yi; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
43 | 2001 | 適用於高速數位用戶迴路之DMT數位IP模組設計及實現 (I) | 吳安宇 | ||||
44 | 2001 | 數位視訊傳輸之前饋式錯誤修正碼之快速雛形機設計技術與 超大型積體電路架構設計(Ⅲ) | 吳安宇 | ||||
45 | 2001 | SOC/IP設計方法與驗證教學研討會執行成果報告 | 吳安宇 | ||||
46 | 2001 | A cost-effective TEQ algorithm for ADSL systems | Wang, Chih-Chi; Wu, An-Yeu ; Wang, Bor-Min | IEEE International Conference on Communications | 0 | 0 | |
47 | 2001 | A unified design framework for vector rotational CORDIC family based on angle quantization process | AN-YEU(ANDY) WU ; Wu, Cheng-Shing | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | 4 | 0 | |
48 | 2001 | Modified Vector Rotational CORDIC (MVR-CORDIC) Algorithm and Architecture | Wu, Cheng-Shing; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 62 | 49 | |
49 | 1995 | FFT VLSI Implementation VLSI Signal Processing | 吳安宇 | ||||
50 | 1989 | Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review | 吳安宇 |