第 1 到 230 筆結果,共 230 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2020 | Weighted pulse decomposition analysis of fingertip photoplethysmogram signals for blood pressure assessment | Chiu-Hua Huang; Yu-Chia Yang; Pei-Yun Tsai; AN-YEU(ANDY) WU ; HUNG-JU LIN ; TZUNG-DAU WANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
2 | 2013 | VLSI implementation of real-time motion compensated beamforming in synthetic transmit aperture imaging | AN-YEU(ANDY) WU ; Ho, K.-Y.; Chen, Y.-H.; Zhan, C.-Z.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
3 | 2004 | VLSI design of dual-mode Viterbi/turbo decoder for 3GPP | Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | |||
4 | 2002 | VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems | AN-YEU(ANDY) WU ; Hsu, H.-Y.; AN-YEU(ANDY) WU | 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 | |||
5 | 2001 | A very low-cost multi-mode Reed Solomon decoder based on Peterson-Gorenstein-Zierler algorithm | Wang, Sheng-Feng; Hsu, Huai-Yi; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
6 | 2015 | Variation-aware core-level redundancy scheme for reliable DSP computation in multi-core systems | AN-YEU(ANDY) WU ; Chu, W.-C.; Li, H.-T.; Chou, C.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
7 | 2008 | Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel | Fan-Min Li; Cheng-Hung Lin; AN-YEU(ANDY) WU ; 吳安宇 | Transactions on Very Large Scale Integration (VLSI) Systems | 12 | 11 | |
8 | 2004 | Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel | Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | 0 | 0 | |
9 | 2020 | An Ultra-Low Latency 7.8-13.6 pJ/b Reconfigurable Neural Network-Assisted Polar Decoder with Multi-Code Length Support | AN-YEU(ANDY) WU | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | |||
10 | 2006 | Ultra low-cost 3.2Gb/s optical-rate reed solomon decoder IC design | AN-YEU(ANDY) WU ; Hsu, H.-Y.; Yeo, J.-C.; AN-YEU(ANDY) WU | 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 | |||
11 | 2004 | Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design | Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
12 | 2014 | Trend-extracted MSE based on adaptive aligned EEMD with early termination scheme | Huang, P.-W.; Jou, W.-J.; Lin, Y.-M.; Jen, H.-I.; SUNG-CHUN TANG ; DAR-MING LAI ; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
13 | 2012 | Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems | AN-YEU(ANDY) WU ; Chen, K.-C.; Chih-Hao; Lin, S.-Y.; Hung, H.-S.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 | |||
14 | 2011 | Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems | AN-YEU(ANDY) WU ; Chao, C.-H.; Yin, T.-C.; Lin, S.-Y.; AN-YEU(ANDY) WU | International System on Chip Conference | |||
15 | 1998 | Transform-domain delayed LMS algorithm and architecture | AN-YEU(ANDY) WU ; Wu, An-Yeu; Wu, Cheng-Shing; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
16 | 2010 | Traffic-thermal mutual-coupling co-simulation platform for three-dimensional network-on-chip | AN-YEU(ANDY) WU ; Jheng, K.-Y.; Chao, C.-H.; Wang, H.-Y.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 | |||
17 | 2012 | Traffic-balanced topology-aware multiple routing adjustment for throttled 3D NoC systems | AN-YEU(ANDY) WU ; Chen, K.-C.; Lin, S.-Y.; Hung, H.-S.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
18 | 2008 | Traffic-Balanced IP Mapping Algorithm for 2D-mesh on-chip-networks | AN-YEU(ANDY) WU ; Lin, T.-J.; Lin, S.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
19 | 2011 | Traffic-and thermal-aware routing for throttled three-dimensional Network-on-Chip systems | AN-YEU(ANDY) WU ; Lin, S.-Y.; Yin, T.-C.; Wang, H.-Y.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 | |||
20 | 2010 | Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems | AN-YEU(ANDY) WU ; Chao, C.-H.; Jheng, K.-Y.; Wang, H.-Y.; Wu, J.-C.; AN-YEU(ANDY) WU | NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip | |||
21 | 2013 | Traffic- and Thermal-aware Adaptive Beltway Routing for three dimensional Network-on-Chip systems | AN-YEU(ANDY) WU ; Chen, K.-C.; Kuo, C.-C.; Hung, H.-S.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
22 | 2017 | Thermal/Traffic Mutual-Coupling Co-simulation Platform for 3D Network-on-Chip (NoC) Designs | An-Yeu (Andy) Wu; Kun-Chih (Jimmy) Chen; Chih-Hao Chao; AN-YEU(ANDY) WU ; 吳安宇 | International Workshop on Network on Chip Architectures (NoCArc'17) | 0 | 0 | |
23 | 2014 | Thermal-aware Dynamic Buffer Allocation for Proactive routing algorithm on 3D Network-on-Chip systems | AN-YEU(ANDY) WU ; Lee, Y.-S.; Hsin, H.-K.; Chen, K.-C.; Chang, E.-J.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 | |||
24 | 2020 | Task-projected hyperdimensional computing for multi-task learning | AN-YEU(ANDY) WU | IFIP Advances in Information and Communication Technology | |||
25 | 2022 | T-EAP: Trainable Energy-Aware Pruning for NVM-based Computing-in-Memory Architecture | Chang, Cheng Yang; YU-CHUAN CHUANG; Chou, Kuang Chao; AN-YEU(ANDY) WU | Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022 | 3 | 0 | |
26 | 2014 | A stroke severity monitoring system based on quantitative modified multiscale entropy | Jou, W.-J.; Huang, P.-W.; Lin, Y.-M.; SUNG-CHUN TANG ; DAR-MING LAI ; AN-YEU(ANDY) WU | IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings | 0 | 0 | |
27 | 2019 | Sparse Autoencoder with Attention Mechanism for Speech Emotion Recognition. | AN-YEU(ANDY) WU ; Sun, Ting-Wei; AN-YEU(ANDY) WU | IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019, Hsinchu, Taiwan, March 18-20, 2019 | |||
28 | 2019 | Sparse Autoencoder with Attention Mechanism for Speech Emotion Recognition | Ting-Wei Sun; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE International Symposium on AI for Circuits and Systems (AICAS-2019) | |||
29 | 2016 | Sniper-TEVR: Core-variation simulation platform with register-level fault injection for robust computing in CMP system | AN-YEU(ANDY) WU ; Chou, C.-Y.; Ho, Y.-C.; Li, H.-T.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 | |||
30 | 2019 | Scattering Multi-Connectivity Estimation For Indoor Mmwave Small Cells Under Limited Training Steps | Hung-Yi Cheng; Ching-Chun Liao; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2019) | 0 | 0 | |
31 | 2004 | A scalable Reed-Solomon decoding processor based on unified finite-field processing element design | Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
32 | 2021 | Scalable NPairLoss-Based Deep-ECG for ECG Verification | AN-YEU(ANDY) WU | IFIP Advances in Information and Communication Technology | |||
33 | 2021 | A scalable extreme learning machine (S-ELM) for class-incremental ECG-based user identification | AN-YEU(ANDY) WU | Proceedings - IEEE International Symposium on Circuits and Systems | |||
34 | 2015 | Scalable compressive sensing-based multi-user detection scheme for Internet-of-Things applications | AN-YEU(ANDY) WU ; Liu, J.; Cheng, H.-Y.; Liao, C.-C.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
35 | 2007 | Robust packet detector based automatic gain control algorithm for OFDM-based ultra-wideband systems | AN-YEU(ANDY) WU ; Chu, N.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
36 | 2016 | Robust LMS-based compressive sensing reconstruction algorithm for noisy wireless sensor networks | Lin, Y.-M.; Kuo, H.-C. ; AN-YEU(ANDY) WU | 2nd International Conference on Intelligent Green Building and Smart Grid | 1 | 0 | |
37 | 2014 | Robust decision feedback equalizer scheme by using sphere-decoding detector | AN-YEU(ANDY) WU ; Cheng, H.-Y.; Chu, C.-Y.; Cheng, Y.-L.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
38 | 2004 | Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme | AN-YEU(ANDY) WU ; Lin, C.-H.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
39 | 2017 | Robust Compressed Analysis Using Subspace-based Dictionary for ECG Telemonitoring Systems | Meng-Ya Tsai; Ching-Yao Chou; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Workshop on Signal Processing Systems (SiPS-2017) | 7 | 0 | |
40 | 2016 | Reliable PPG-based Algorithm in Atrial Fibrillation Detection | Shih-Ming Shan; Sung-Chun Tang; Pei-Wen Huang; Yu-Min Lin,Wei-Han Huang; Dar-Ming Lai; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE BioMedical Circuits and Systems Conference | 8 | 0 | |
41 | 2017 | Reliable Compressive Sensing (CS)-based Multi-User Detection with Power-based Zadoff-Chu Sequence Design | Chieh-Fang Teng; Ching-Chun Liao; Hung-Yi Cheng; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Workshop on Signal Processing Systems (SiPS-2017) | 4 | 0 | |
42 | 2010 | Regional ACO-based routing for load-balancing in NoC systems | AN-YEU(ANDY) WU ; Hsin, H.-K.; Chang, E.-J.; Chao, C.-H.; AN-YEU(ANDY) WU | 2nd World Congress on Nature and Biologically Inspired Computing, NaBIC 2010 | |||
43 | 2007 | Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems. | Yu, Tzu-Hao; Sun, Shih-Yu; Ding, Chih-Liang; Li, Pai-Chi; Wu, An-Yeu; PAI-CHI LI ; AN-YEU(ANDY) WU | Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China | 8 | 0 | |
44 | 2006 | Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems | AN-YEU(ANDY) WU ; Lee, Y.-H.; Yu, T.-H.; Huang, K.-K.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS | |||
45 | 2017 | Progressive Channel Estimation for Ultra-Low Latency Millimeter-wave Communications | Hung-Yi Cheng; Ching-Chun Liao; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Global Conference on Signal and Information Processing | 4 | 0 | |
46 | 2017 | Profiling and SW/HW Co-design for Efficient SDN/OpenFlow Data Plane Realization | Ching-Che Wang; Yi-Ta Chen; Ding-Yuan Lee; Sheng-Chun Kao; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE International Conference on Electronics Information and Emergency Communication (ICEIEC) | 0 | 0 | |
47 | 2013 | Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems. | AN-YEU(ANDY) WU ; Kuo, Che-Chuan; Chen, Kun-Chih; Chang, En-Jui; AN-YEU(ANDY) WU | 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013 | |||
48 | 2013 | Proactive thermal-budget-based beltway routing algorithm for thermal-aware 3D NoC systems | AN-YEU(ANDY) WU ; Kuo, C.-C.; Chen, K.-C.; Chang, E.-J.; AN-YEU(ANDY) WU | 2013 International Symposium on System-on-Chip, SoC 2013 | |||
49 | 2015 | Predicting stroke outcomes based on multi-modal analysis of physiological signals | Huang, Pei-Wen; SUNG-CHUN TANG ; Lin, Yu-Min; Liu, You-Cheng; Jou, Wei-Jung; Jen, Hsiao-I; DAR-MING LAI ; AN-YEU(ANDY) WU | International Conference on Digital Signal Processing, DSP | 0 | 0 | |
50 | 2021 | PQ-HDC: Projection-Based Quantization Scheme for Flexible and Efficient Hyperdimensional Computing | AN-YEU(ANDY) WU | IFIP Advances in Information and Communication Technology | |||
51 | 2007 | A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. | AN-YEU(ANDY) WU ; Chao, Chih-Hao; Kuo, Yen-Lin; Wu, An-Yeu; Chien, Weber; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | |||
52 | 2008 | Power efficient low latency survivor memory architecture for viterbi decoder | AN-YEU(ANDY) WU ; Chu, C.-Y.; Huang, Y.-C.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | |||
53 | 2006 | A portable all-digital pulsewidth control loop for SOC applications | Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
54 | 2005 | Polar transmitter for wireless communication system | Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai ; Jheng, Kai-Yuan; Wu, An-Yeu | 2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005 | 0 | 0 | |
55 | 2019 | Polar feature based deep architectures for automatic modulation classification considering channel fading | AN-YEU(ANDY) WU | 2018 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2018 - Proceedings | |||
56 | 2018 | Polar Feature based Deep Architecture for Automatic Modulation Classification Considering Channel Fading | Chieh-Fang Teng; Ching-Chun Liao; Chun-Hsiang Chen; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Global Conference on Signal and Information Processing (GlobalSIP’18) | 17 | 0 | |
57 | 2012 | Path-diversity-aware adaptive routing in network-on-chip systems | AN-YEU(ANDY) WU ; Kuo, Y.-H.; Tsai, P.-A.; Ho, H.-P.; Chang, E.-J.; Hsin, H.-K.; AN-YEU(ANDY) WU | IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012 | |||
58 | 1995 | Parallel programmable video co-processor design. | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K. J. Ray; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995 | |||
59 | 1996 | Parallel programmable video co-processor design | AN-YEU(ANDY) WU ; Wu, An-Yeu; Ray Liu, K.J.; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE International Conference on Image Processing | |||
60 | 2009 | PAC Duo SoC performance analysis with ESL design methodology | AN-YEU(ANDY) WU ; Chuang, I.-Y.; Chang, C.-W.; Fan, T.-Y.; Yeh, J.-C.; Ji, K.-M.; Ma, J.-L.; Wu, A.-Y.; Lin, S.-Y.; AN-YEU(ANDY) WU | ASICON 2009 - 8th IEEE International Conference on ASIC | |||
61 | 2008 | Overview of ITRI PAC project - From VLIW DSP processor to multicore computing platform | AN-YEU(ANDY) WU ; Lin, T.-J.; Liu, C.-N.; Tseng, S.-Y.; Chu, Y.-H.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | |||
62 | 2017 | Overview of High-Efficiency Ant Colony Optimization (ACO)-based Adaptive Routings for Traffic Balancing in Network-on-Chip Systems | En-Jui Chang; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE 12th International Conference on ASIC (ASICON-2017) | 4 | 0 | |
63 | 2018 | Overview of Efficient Compressive Sensing Reconstruction Engines for E-Health Applications | Ting-Sheng Chen; Kai-Ni Hou; Yo-Woei Pua; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT’18) | 0 | 0 | |
64 | 1998 | Optimal fixed-point VLSI structure of a floating-point based digital filter design | AN-YEU(ANDY) WU ; Wu, An-Yeu; Hwang, Kuo-Fuo; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
65 | 2020 | Online Extreme Learning Machine Design for the Application of Federated Learning | AN-YEU(ANDY) WU | Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020 | |||
66 | 2006 | On-line MSR-cordic VLSI architecture with applications to cost-efficient rotation-based adaptive filtering systems | AN-YEU(ANDY) WU ; Yu, T.-H.; Yu, C.-L.; Jheng, K.-Y; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS | |||
67 | 2007 | On the fixed-point properties of mixed-scaling-rotation cordic algorithm | AN-YEU(ANDY) WU ; Yu, C.-L.; Yu, T.-H.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
68 | 2001 | A novel trellis-based searching scheme for EEAS-based CORDIC algorithm. | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; AN-YEU(ANDY) WU | IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2001, 7-11 May, 2001, Salt Palace Convention Center, Salt Lake City, Utah, USA, Proceedings | |||
69 | 1999 | A novel multirate adaptive FIR filtering algorithm and structure. | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; AN-YEU(ANDY) WU | Proceedings of the 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '99, Phoenix, Arizona, USA, March 15-19, 1999 | |||
70 | 2002 | A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; AN-YEU(ANDY) WU | Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002 | |||
71 | 2005 | A new stopping criterion for efficient early termination in turbo decoder designs | Li, Fan-Min; Wu, An-Yeu | 2005 International Symposium on Intelligent Signal Processing and Communication Systems | 0 | 0 | |
72 | 2002 | A new pipelined adaptive DFE architecture with improved convergence rate | Yang, Meng-Da; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
73 | 2007 | A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. | AN-YEU(ANDY) WU ; Shen, Wein-Tsung; Chao, Chih-Hao; Lien, Yu-Kuang; AN-YEU(ANDY) WU | First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings | |||
74 | 2019 | Neural network-based equalizer by utilizing coding gain in advance | AN-YEU(ANDY) WU | GlobalSIP 2019 - 7th IEEE Global Conference on Signal and Information Processing, Proceedings | |||
75 | 2020 | A neural network-aided viterbi receiver for joint equalization and decoding | AN-YEU(ANDY) WU | IEEE International Workshop on Machine Learning for Signal Processing, MLSP | |||
76 | 2020 | Neural Network-Aided BCJR Algorithm for Joint Symbol Detection and Channel Decoding | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
77 | 2004 | Multiplierless multirate decimator / interpolator module generator | AN-YEU(ANDY) WU ; Jou, S.-J.; Jheng, K.-Y.; Chen, H.-Y.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | |||
78 | 2016 | Multilevel-DFT based Low-Complexity Hybrid Precoding for Millimeter Wave MIMO Systems | Yu-Hsin Liu; Chiang-Hen Chen; Cheng-Rung Tsai; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Conference on Signal Processing, Communications and Computing (ICSPCC2016) | 3 | 0 | |
79 | 2007 | Multilevel LINC system design for wireless transmitters | Chen, Y.-J.; Jheng, K.-Y.; Wu, A.-Y.; Tsao, H.-W.; Tzeng, B.; HEN-WAI TSAO ; AN-YEU(ANDY) WU | 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 | |||
80 | 2007 | Multilevel LINC system design for power efficiency enhancement | AN-YEU(ANDY) WU ; Jheng, K.-Y.; Chen, Y.-J.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
81 | 2010 | Multi-prediction particle filter for effcient memory utilization | AN-YEU(ANDY) WU ; Chu, C.-Y.; Chao, C.-H.; Chao, M.-A.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
82 | 2011 | Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon | AN-YEU(ANDY) WU ; Hsin, H.-K.; Chang, E.-J.; Chao, C.-H.; Lin, S.-Y.; AN-YEU(ANDY) WU | International System on Chip Conference | |||
83 | 1993 | Multi-layer 2-D adaptive filtering architecture based on McClellan transformation | AN-YEU(ANDY) WU ; Liu, K.J.Ray; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
84 | 2010 | Motion-tracking adaptive persistence and adaptive-size median filter for color doppler processing in ultrasound systems on multicore platform | Zhan, C.-Z.; Chang, K.-T.; Chen, Y.-H.; Li, P.-C.; AN-YEU(ANDY) WU ; PAI-CHI LI | 2010 IEEE Biomedical Circuits and Systems Conference, BioCAS 2010 | 2 | 0 | |
85 | 2013 | Motion artifact elimination algorithm with eigen-based clutter filter for color Doppler processing | AN-YEU(ANDY) WU ; Liu, Z.-L.; Chen, Y.-H.; Zhan, C.-Z.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
86 | 2000 | Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT. | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings | |||
87 | 2000 | Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
88 | 2003 | Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-perforance rotatioal operations | AN-YEU(ANDY) WU ; Lin, Z.-X.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
89 | 2023 | Mitigating Non-ideality Issues of Analog Computing-In-Memory in DNN-based designs | Huang, Chi Tse; AN-YEU(ANDY) WU | Proceedings of International Conference on ASIC | |||
90 | 2008 | Low-power traceback MAP decoding for double-binary convolutional turbo decoder | AN-YEU(ANDY) WU ; Lin, C.-H.; Chen, C.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
91 | 1996 | Low-power design methodology for DSP systems using multirate approach | AN-YEU(ANDY) WU ; Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
92 | 1994 | A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994 | |||
93 | 1994 | Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
94 | 2017 | Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine | Chia-Heng Wu; Ting-Sheng Chen; Ding-Yuan Lee; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | Int. Symp. VLSI Design, Automation, and Test | 2 | 0 | |
95 | 2007 | Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. | AN-YEU(ANDY) WU ; Ye, Jhao-Ji; Chen, You-Gang; Wey, I-Chyn; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | |||
96 | 2007 | Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules | AN-YEU(ANDY) WU ; Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
97 | 2018 | Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving | Kai-Ni Hou; Ting-Sheng Chen; Hung-Chi Kuo; Tzu-Hsuan Chen; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2018) | 1 | 0 | |
98 | 2019 | Low-Complexity Recurrent Neural Network-Based Polar Decoder With Weight Quantization Mechanism | Chieh-Fang Teng; Chen-Hsi (Derek) Wu; rew Kuan-Shiuan Ho; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2018) | 11 | 0 | |
99 | 2020 | Low-Complexity LSTM-Assisted Bit-Flipping Algorithm for Successive Cancellation List Polar Decoder | AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | |||
100 | 2015 | Low-complexity hybrid precoding algorithm based on orthogonal beamforming codebook | AN-YEU(ANDY) WU ; Hung, W.-L.; Chen, C.-H.; Liao, C.-C.; Tsai, C.-R.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
101 | 2019 | Low-Complexity Compressive Analysis in Sub-Eigenspace for ECG Telemonitoring System | Ching-Yao Chou; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2018) | 1 | 0 | |
102 | 2018 | Low-Complexity Compressed Analysis in Eigenspace with Limited Labeled Data for Real-Time Electrocardiography Telemonitoring | Kai-Chieh Hsu; Bo-Hong Cho; Ching-Yao Chou; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Global Conference on Signal and Information Processing (GlobalSIP’18) | 3 | 0 | |
103 | 2019 | Low-complexity compressed analysis in eigenspace with limited labeled data for real-time electrocardiography telemonitoring | AN-YEU(ANDY) WU | 2018 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2018 - Proceedings | |||
104 | 2020 | Low-Complexity Compressed Alignment-Aided Compressive Analysis for Real-Time Electrocardiography Telemonitoring | AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | |||
105 | 2015 | "Low Memory-Cost Scramble Methods for Constructing Deterministic CS Matrixs | AN-YEU(ANDY) WU ; AN-YEU(ANDY) WU | ||||
106 | 2015 | Low memory-cost scramble methods for constructing deterministic CS matrix | AN-YEU(ANDY) WU ; Zhang, J.-F.; Geng, J.; Lin, Y.-M.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
107 | 2005 | Low cost decision feedback equalizer (DFE) design for giga-bit systems | AN-YEU(ANDY) WU ; Lin, C.-H.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
108 | 2008 | Location-constrained particle filter for rssi-based indoor human positioning and tracking system | AN-YEU(ANDY) WU ; Chao, C.-H.; Chu, N.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
109 | 2014 | LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems | AN-YEU(ANDY) WU ; Chen, K.-C.; Li, H.-T.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 | |||
110 | 2022 | Learnable Mixed-precision and Dimension Reduction Co-design for Low-storage Activation | Tai, Yu Shan; Chang, Cheng Yang; Teng, Chieh Fang; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
111 | 2010 | Joint-decision adaptive clutter filter and motion-tracking adaptive persistence for color doppler processing in ultrasonic systems | AN-YEU(ANDY) WU ; Chang, K.-T.; Zhan, C.-Z.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
112 | 2017 | Joint Spatially Sparse Channel Estimation for Millimeter-wave Cellular Systems | Cheng-Rung Tsai; Chiang-Hen Chen; Yu-Hsin Liu; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Global Conference on Signal and Information Processing | 1 | 0 | |
113 | 2016 | Joint RF/Baseband Grouping-based Codebook Design for Hybrid Beamforming in mmWave MIMO Systems | Chien-Sheng Wu; Chiang-Hen Chen; Cheng-Rung Tsai; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Conference on Signal Processing, Communications and Computing (ICSPCC2016) | 2 | 0 | |
114 | 2020 | IP-HDC: Information-Preserved Hyperdimensional Computing for Multi-Task Learning | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
115 | 2001 | An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. | AN-YEU(ANDY) WU ; Yu, Chi-Li; AN-YEU(ANDY) WU | Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001 | |||
116 | 2003 | Implementation of a programmable 64?2048-point FFT/IFFT processor for OFDM-based communication systems | AN-YEU(ANDY) WU ; Kuo, J.-C.; Wen, C.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
117 | 2019 | Hyperdimensional Computing-based Multimodality Emotion Recognition with Physiological Signals. | AN-YEU(ANDY) WU ; Chang, En-Jui; Rahimi, Abbas; Benini, Luca; AN-YEU(ANDY) WU | IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019, Hsinchu, Taiwan, March 18-20, 2019 | |||
118 | 2019 | Hyperdimensional Computing-based Multimodality Emotion Recognition with Physiological Signals | En-Jui Chang; Abbas Rahimi; Luca Benini; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE International Symposium on AI for Circuits and Systems (AICAS-2019) | |||
119 | 2021 | Hyperdimensional Computing with Learnable Projection for User Adaptation Framework | AN-YEU(ANDY) WU | IFIP Advances in Information and Communication Technology | |||
120 | 2013 | Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems | AN-YEU(ANDY) WU ; Tsai, P.-A.; Kuo, Y.-H.; Chang, E.-J.; Hsin, H.-K.; AN-YEU(ANDY) WU | 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 | |||
121 | 2015 | http://access.ee.ntu.edu.tw/Publications/Conference/CA136_2015.pdf | AN-YEU(ANDY) WU ; AN-YEU(ANDY) WU | ||||
122 | 2014 | High-throughput QC-LDPC decoder with cost-effective early termination scheme for non-volatile memory systems | AN-YEU(ANDY) WU ; Lin, Y.-M.; Chen, Y.-H.; Chung, M.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
123 | 2008 | High-throughput dual-mode single/double binary map processor design for wireless wan | AN-YEU(ANDY) WU ; Chen, C.-Y.; Lin, C.-H.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
124 | 2008 | High-throughput 12-mode CTC decoder for WiMAX standard | AN-YEU(ANDY) WU ; Lin, C.-H.; Chen, C.-Y.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | |||
125 | 2008 | High-performance scheduling algorithm for partially parallel LDPC decoder | AN-YEU(ANDY) WU ; Zhan, C.-Z.; Shih, X.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
126 | 2002 | High-performance adaptive decision feedback equalizer based on predictive parallel branch slicer scheme | Yang, Meng-Da; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
127 | 2009 | High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems | AN-YEU(ANDY) WU ; Zhan, C.-Z.; Jheng, K.-Y.; Chen, Y.-L.; Jheng, T.-J.; AN-YEU(ANDY) WU | 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 | |||
128 | 2015 | High performance adaptive routing for Network-on-Chip systems with express highway mechanism | AN-YEU(ANDY) WU ; Lin, S.-C.; Chang, E.-J.; Chen, Y.-Y.; Hsin, H.-K.; AN-YEU(ANDY) WU | IEEE Asia-Pacific Conference on Circuits and Systems | |||
129 | 2006 | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time | Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
130 | 2012 | Foreword | AN-YEU(ANDY) WU ; Wu, A.-Y.; Wang, L.-C.; AN-YEU(ANDY) WU | 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 | |||
131 | 2021 | FL-HDC: Hyperdimensional Computing Design for the Application of Federated Learning | AN-YEU(ANDY) WU | 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021 | |||
132 | 2016 | Filter-based dual-voltage architecture for low-power long-word TCAM design | Chen, T.-S.; Lee, D.-Y.; Liu, T.-T.; AN-YEU(ANDY) WU ; TSUNG-TE LIU | Proceedings of the 2nd International Conference on Intelligent Green Building and Smart Grid, IGBSG 2016 | 4 | 0 | |
133 | 2019 | Feature Selection Framework for XGBoost Based on Electrodermal Activity in Stress Detection | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
134 | 2022 | FACE RECOGNITION FOR FISHEYE IMAGES | Lo, Yi Cheng; Huang, Chiao Chun; Tsai, Yueh Feng; Lo, I. Chan; AN-YEU(ANDY) WU ; HOMER H. CHEN | Proceedings - International Conference on Image Processing, ICIP | 1 | 0 | |
135 | 2020 | Explainable Deep Neural Network for Identifying Cardiac Abnormalities Using Class Activation Map | AN-YEU(ANDY) WU | Computing in Cardiology | |||
136 | 2018 | Error-Resilient Reconfigurable Boosting Extreme Learning Machine for ECG Telemonitoring Systems | Sheng-Hui Wang; Huai-Ting Li; An-Yeu Andy Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE International Symposium on Circuits and Systems (ISCAS-2018) | 6 | 0 | |
137 | 2018 | Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals | Kuan Tung; Po-Kang Liu; Yu-Chuan Chuang; Sheng-Hui Wang; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES’18) | 26 | 0 | |
138 | 2019 | Entropy-assisted multi-modal emotion recognition framework based on physiological signals | AN-YEU(ANDY) WU | 2018 IEEE EMBS Conference on Biomedical Engineering and Sciences, IECBES 2018 - Proceedings | |||
139 | 2018 | Entropy-Assisted Emotion Recognition of Valence and Arousal Using XGBoost Classifier | Sheng-Hui Wang; Huai-Ting Li; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | 14th International Conference on Artificial Intelligence Applications and Innovations (AIAI’18) | 27 | 0 | |
140 | 2019 | Entropy and Complexity Assisted EEG-based Mental Workload Assessment System | AN-YEU(ANDY) WU | BioCAS 2019 - Biomedical Circuits and Systems Conference, Proceedings | |||
141 | 2007 | Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. | AN-YEU(ANDY) WU ; Rao, Huifei; Chen, Jie; Yu, Changhong; Ang, Woon Tiong; Wey, I-Chyn; Wu, An-Yeu; Zhao, Hong; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | |||
142 | 2007 | Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design | AN-YEU(ANDY) WU ; Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
143 | 2008 | Energy-effective design & implementation of an embedded VLIW DSP | AN-YEU(ANDY) WU ; Hsieh, T.-W.; Hsiao, P.-C.; Liao, C.-Y.; Hsieh, H.-C.; Lin, H.-L.; Lin, T.-J.; Chu, Y.-H.; AN-YEU(ANDY) WU | 2008 International SoC Design Conference, ISOCC 2008 | |||
144 | 2010 | Efficient parallelized particle filter design on CUDA | AN-YEU(ANDY) WU ; Chao, M.-A.; Chu, C.-Y.; Chao, C.-H.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
145 | 2021 | Efficient Mind-wandering Detection System with GSR Signals on MM-SART Database | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
146 | 2020 | ECG-Aided PPG Signal Quality Assessment (SQA) System for Heart Rate Estimation | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
147 | 2020 | Dynamic Hyperdimensional Computing for Improving Accuracy-Energy Efficiency Trade-Offs | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
148 | 2015 | Dynamic group allocation reconstruction for group sparse signals | AN-YEU(ANDY) WU ; Tu, Y.-M.; Chang, M.C.; Lin, Y.-M.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
149 | 2007 | Dynamic channel flow control of networks-on-chip systems for high buffer efficiency | AN-YEU(ANDY) WU ; Wu, S.-T.; Chao, C.-H.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
150 | 2003 | Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems | AN-YEU(ANDY) WU ; Chen, P.-H.; Kai-Huang; Hsueh, N.-H.; AN-YEU(ANDY) WU | IEEE International SOC Conference, SOCC 2003 | |||
151 | 2006 | DSP engine design for LINC wireless transmitter systems. | Jheng, Kai-Yuan; Wang, Yi-Chiuan; Wu, An-Yeu; HEN-WAI TSAO ; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece | 0 | 0 | |
152 | 2006 | DSP engine design for LINC wireless transmitter systems | AN-YEU(ANDY) WU ; Jheng, K.-Y.; Wang, Y.-C.; Wu, A.-Y.; Tsao, H.-W.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
153 | 2005 | Digital signal processing engine design for polar transmitter in wireless communication systems | AN-YEU(ANDY) WU ; Ko, H.-Y.; Wang, Y.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
154 | 2011 | Design of transport layer assisted routing for thermal-aware 3D Network-on-Chip | AN-YEU(ANDY) WU ; Yin, T.-C.; Chao, C.-H.; Lin, S.-Y.; AN-YEU(ANDY) WU | APSIPA ASC 2011 - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference 2011 | |||
155 | 2013 | Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems | AN-YEU(ANDY) WU ; Chen, K.-C.; Lin, S.-Y.; AN-YEU(ANDY) WU | 2013 International Symposium on VLSI Design, Automation, and Test | |||
156 | 2000 | Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem. | AN-YEU(ANDY) WU ; Leu, Jye-Jong; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings | |||
157 | 2000 | Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem | AN-YEU(ANDY) WU ; Leu, Jye-Jong; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
158 | 2004 | A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. | AN-YEU(ANDY) WU ; Jheng, Kai-Yuan; Jou, Shyh-Jye; AN-YEU(ANDY) WU | Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004 | |||
159 | 1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology. | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98, Seattle, Washington, USA, May 12-15, 1998 | |||
160 | 1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
161 | 2001 | Cost-efficient multiplier-less FIR filter structure based on modified decor transformation | AN-YEU(ANDY) WU ; Lee, I.-H.; Wu, C.-S.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
162 | 2001 | A cost-effective TEQ algorithm for ADSL systems | Wang, Chih-Chi; Wu, An-Yeu ; Wang, Bor-Min | IEEE International Conference on Communications | 0 | 0 | |
163 | 2013 | Cost-effective scalable QC-LDPC decoder designs for non-volatile memory systems | AN-YEU(ANDY) WU ; Chung, M.-H.; Lin, Y.-M.; Zhan, C.-Z.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
164 | 2008 | Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system | AN-YEU(ANDY) WU ; Chen, Y.-L.; Zhan, C.-Z.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
165 | 2010 | Cost-effective constrained particle filter for indoor localization | AN-YEU(ANDY) WU ; Chao, C.-H.; Chu, C.-Y.; Chao, M.-A.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
166 | 2021 | Convolutional neural network-aided bit-flipping for Belief propagation decoding of polar codes | AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | |||
167 | 1998 | Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
168 | 2015 | Compressive sensing based ECG telemonitoring with personalized dictionary basis | Lin, Y.-M.; Chen, Y.; Kuo, H.-C.; AN-YEU(ANDY) WU ; HUNG-CHI KUO | IEEE Biomedical Circuits and Systems Conference (BioCAS-2015) | 8 | 0 | |
169 | 2015 | Compressive sensing based ECG telemonitoring with personalized dictionary basis | Yu-Min Lin; Yi Chen; Hung-Chi Kuo; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Biomedical Circuits and Systems Conference (BioCAS-2015) | 7 | 0 | |
170 | 2017 | Compressive Sensing Based ECG Monitoring With Effective AF Detection | Hung-Chi Kuo; Yu-Min Lin; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2017) | 6 | 0 | |
171 | 2012 | Coherent image herding of inhomogeneous motion compensation for synthetic transmit aperture in ultrasound image | AN-YEU(ANDY) WU ; Chen, Y.-H.; Ho, K.-Y.; Zhan, C.-Z.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
172 | 2019 | Co-Design of Sparse Coding and Dictionary Learning for Real-Time Physiological Signals Monitoring | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
173 | 2022 | C3-SL: Circular Convolution-Based Batch-Wise Compression for Communication-Efficient Split Learning | Hsieh, Cheng Yen; YU-CHUAN CHUANG; AN-YEU(ANDY) WU | IEEE International Workshop on Machine Learning for Signal Processing, MLSP | 1 | 0 | |
174 | 2024 | BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator | Chang, Cheng Yang; Huang, Chi Tse; YU-CHUAN CHUANG; Chou, Kuang Chao; AN-YEU(ANDY) WU | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | |||
175 | 2022 | Automated Quantization Range Mapping for DAC/ADC Non-linearity in Computing-In-Memory | Huang, Chi Tse; YU-CHUAN CHUANG; Lin, Ming Guang; AN-YEU(ANDY) WU | Proceedings - IEEE International Symposium on Circuits and Systems | 1 | 0 | |
176 | 2004 | Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems | Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu | IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 0 | 0 | |
177 | 2003 | Angle quantization approach for lattice IIR filter implementation and its trellis de-allocation algorithm | Wu, An-Yeu ; Lee, I-Hsien; Wu, Cheng-Shing | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | 0 | 0 | |
178 | 2001 | An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter | AN-YEU(ANDY) WU ; Yu, C.-L.; AN-YEU(ANDY) WU | Materials Research Society Symposium | |||
179 | 2008 | An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation | AN-YEU(ANDY) WU ; Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
180 | 2015 | An algorithmic error-resilient scheme for robust LDPC decoding | AN-YEU(ANDY) WU ; Li, H.-T.; Lee, D.-Y.; Chen, K.-C.; AN-YEU(ANDY) WU | 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 | |||
181 | 1994 | Algorithms and architectures for split recursive least squares | AN-YEU(ANDY) WU ; Liu, K.J.Ray; AN-YEU(ANDY) WU | IEEE Workshop on VLSI Signal Processing | |||
182 | 1995 | Algorithm-based low-power transform coding architectures. | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995 | |||
183 | 1995 | Algorithm-based low-power transform coding architectures | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
184 | 1995 | Algorithm-based low-power DSP system design: Methodology and verification | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE Workshop on VLSI Signal Processing | |||
185 | 2011 | Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems | AN-YEU(ANDY) WU ; Zhan, C.-Z.; Liu, Z.-L.; AN-YEU(ANDY) WU | 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 | |||
186 | 2015 | Adaptive filter-based reconstruction engine design for compressive sensing | AN-YEU(ANDY) WU ; Huang, N.-S.; Lin, Y.-M.; Chen, Y.; AN-YEU(ANDY) WU | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | |||
187 | 2019 | AdaBoost-Assisted Extreme Learning Machine for Efficient Online Sequential Classification | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
188 | 2013 | ACO-based fault-aware routing algorithm for Network-on-Chip systems. | AN-YEU(ANDY) WU ; Lin, Chia-An; Hsin, Hsien-Kai; Chang, En-Jui; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS 2013, Taipei City, Taiwan, October 16-18, 2013 | |||
189 | 2013 | ACO-based fault-aware routing algorithm for Network-on-Chip systems | AN-YEU(ANDY) WU ; Lin, C.-A.; Hsin, H.-K.; Chang, E.-J.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
190 | 2012 | ACO-based Deadlock-Aware fully-adaptive routing in Network-on-Chip systems | AN-YEU(ANDY) WU ; Su, K.-Y.; Hsin, H.-K.; Chang, E.-J.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
191 | 2010 | ACO-based cascaded adaptive routing for traffic balancing in NoC systems | AN-YEU(ANDY) WU ; Chang, E.-J.; Chao, C.-H.; Jheng, K.-Y.; Hsin, H.-K.; AN-YEU(ANDY) WU | 1st International Conference on Green Circuits and Systems | |||
192 | 2013 | Accelerating motion-compensated adaptive color Doppler engine on CUDA-based GPU platform. | AN-YEU(ANDY) WU ; Lee, I-Hsuan; Chen, Yu-Hao; Huang, Nai-Shan; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS 2013, Taipei City, Taiwan, October 16-18, 2013 | |||
193 | 2013 | Accelerating motion-compensated adaptive color Doppler engine on CUDA-based GPU platform | AN-YEU(ANDY) WU ; Lee, I.-H.; Chen, Y.-H.; Huang, N.-S.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
194 | 2004 | Academia-industry collaboration in SoC design education: Wishes and reality | AN-YEU(ANDY) WU ; Mashiko, K.; Kanuma, A.; Kozawa, T.; Lee, K.; Wu, A.; Wang, Z.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | |||
195 | 2008 | A universal look-ahead algorithm for pipelining IIR filters | AN-YEU(ANDY) WU ; Chen, Y.-L.; Chen, C.-Y.; Jheng, K.-Y.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test | |||
196 | 2006 | A triple-mode MAP/VA IP design for advanced wireless communication systems | AN-YEU(ANDY) WU ; Lin, C.-H.; Li, F.-M.; Shi, X.-Y.; AN-YEU(ANDY) WU | 2005 IEEE Asian Solid-State Circuits Conference | |||
197 | 2009 | A triple-mode LDPC decoder design for IEEE 802.11n system | AN-YEU(ANDY) WU ; Chao, M.-A.; Wen, J.-Y.; Shih, X.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
198 | 2006 | A Shortened Impulse Response Filter (SIRF) scheme for cost-effective echo canceller design of 10GBase-T ethernet system | AN-YEU(ANDY) WU ; Hsu, M.-F.; Chen, Y.-L.; Jheng, K.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | |||
199 | 2005 | A scalable DCO design for portable ADPLL designs | AN-YEU(ANDY) WU ; Wu, C.-T.; Wang, W.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
200 | 2009 | A scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems | AN-YEU(ANDY) WU ; Lin, S.-Y.; Hsu, C.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
201 | 2006 | A robust band-tracking packet detector (BT-PD) in OFDM-based ultra-wideband systems | AN-YEU(ANDY) WU ; Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | |||
202 | 2009 | A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices | AN-YEU(ANDY) WU ; Shih, X.-Y.; Zhan, C.-Z.; AN-YEU(ANDY) WU | 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 | |||
203 | 2007 | A power-aware reconfigurable rendering engine design with 453MPixels/s, 16.4MTriangles/s performance | AN-YEU(ANDY) WU ; Chao, C.-H.; Kuo, Y.-L.; Wu, A.-Y.; Chien, W.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
204 | 2001 | A novel Trellis-based searching scheme for EEAS-based CORDIC algorithm | AN-YEU(ANDY) WU ; Wu, C.-S.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
205 | 2003 | A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation | AN-YEU(ANDY) WU ; Lai, J.-T.; Wu, A.-Y.; Yeh, C.-C.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
206 | 2002 | A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller | AN-YEU(ANDY) WU ; Wu, C.-S.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
207 | 2006 | A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment | AN-YEU(ANDY) WU ; Chen, Y.-G.; Wey, I.-C.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference | |||
208 | 2006 | A new early termination scheme of iterative turbo decoding using decoding threshold | AN-YEU(ANDY) WU ; Li, F.-M.; Lin, C.-H.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | |||
209 | 2007 | A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network | AN-YEU(ANDY) WU ; Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; AN-YEU(ANDY) WU | NOCS 2007: First International Symposium on Networks-on-Chip | |||
210 | 2005 | A memory-reduced Log-MAP kernel for turbo decoder | AN-YEU(ANDY) WU ; Tsai, T.-H.; Lin, C.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
211 | 2012 | A low-complexity grouping FFT-based codebook searching algorithm in LTE system | AN-YEU(ANDY) WU ; Lin, Y.-H.; Zhan, C.-Z.; Chu, C.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
212 | 2006 | A low cost packet detector in OFDM-based ultra-wideband systems | AN-YEU(ANDY) WU ; Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | |||
213 | 2005 | A high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T.; Wang, W.; AN-YEU(ANDY) WU | 2005 PhD Research in Microelectronics and Electronics | |||
214 | 2004 | A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design | AN-YEU(ANDY) WU ; Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | |||
215 | 2005 | A DVB-T baseband demodulator design based on multimode silicon IPs | AN-YEU(ANDY) WU ; Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; AN-YEU(ANDY) WU | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test | |||
216 | 2004 | A design flow for multiplierless linear-phase fir filters: From system specification to verilog code | AN-YEU(ANDY) WU ; Jheng, K.-Y.; Jou, S.-J.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
217 | 2007 | A clock-fault tolerant architecture and circuit for reliable nanoelectronics system | AN-YEU(ANDY) WU ; Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU | 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 | |||
218 | 2009 | A channel-adaptive early termination strategy for LDPC decoders | AN-YEU(ANDY) WU ; Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
219 | 2008 | A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications | AN-YEU(ANDY) WU ; Shih, X.-Y.; Zhan, C.-Z.; AN-YEU(ANDY) WU | 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | |||
220 | 2009 | A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications | AN-YEU(ANDY) WU ; Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; AN-YEU(ANDY) WU | Asia and South Pacific Design Automation Conference, ASP-DAC | |||
221 | 2005 | A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
222 | 2010 | A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system | AN-YEU(ANDY) WU ; Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; AN-YEU(ANDY) WU | ESSCIRC 2010 - 36th European Solid State Circuits Conference | |||
223 | 2007 | A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system | AN-YEU(ANDY) WU ; Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; AN-YEU(ANDY) WU | IEEE Symposium on VLSI Circuits | |||
224 | 2015 | A 1.96 mm 2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols | CHEN-MOU CHENG ; AN-YEU(ANDY) WU ; CR Tsai; MC Hsiao; WC Shen; AYA Wu; CHEN-MOU CHENG ; AN-YEU(ANDY) WU | 2015 IEEE International Symposium on Circuits and Systems (ISCAS) | |||
225 | 2011 | A 0.16nJ/bit/iteration 3.38mm 2 turbo decoder chip for WiMAX/LTE standards | AN-YEU(ANDY) WU ; Lin, C.-H.; Chen, C.-Y.; Chang, E.-J.; AN-YEU(ANDY) WU | 2011 International Symposium on Integrated Circuits | |||
226 | 2007 | A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2007 IEEE Asian Solid-State Circuits Conference | |||
227 | 0 | a | a; AN-YEU(ANDY) WU ; 吳安宇 | ||||
228 | 2018 | A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring | Ting-Sheng Chen; Hung-Chi Kuo; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE International Solid-State Circuits Conference (ISSCC) | 9 | 0 | |
229 | 2004 | 1000BASE-T Gigabit Ethernet baseband DSP IC design | Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | |||
230 | 2006 | A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 |