Publications

Results 1-151 of 151 (Search time: 0.018 seconds).

Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12022Low-IR-Drop Test Pattern Regeneration Using A Fast PredictorLiu, Shi Tang; Chen, Jia Xian; Wu, Yu Tsung; Hsieh, Chao Ho; CHIEN-MO LI ; Chang, Norman; Li, Ying Shiun; Chuang, Wen TzeProceedings - International Symposium on Quality Electronic Design, ISQED00
22021Fault Modeling and Testing of Spiking Neural Network ChipsHsieh, Yi Zhan; Tseng, Hsiao Yin; Chiu, I. Wei; CHIEN-MO LI Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 202120
32021Improving Volume Diagnosis and Debug with Test Failure Clustering and ReorganizationWu M.-T; Kuo C.-S; Li J.C.-M; Nigh C; Bhargava G.; CHIEN-MO LI Proceedings - International Test Conference00
42021Minimum Operating Voltage Prediction in Production Test Using Accumulative LearningKuo Y.-T; Lin W.-C; Chen C; Hsieh C.-H; Li J.C.-M; Jia-Wei Fang E; Hsueh S.S.-Y.; CHIEN-MO LI Proceedings - International Test Conference10
52021Clock-Less DFT and BIST for Dual-Rail Asynchronous CircuitsChen T.-C; Pai C.-C; Hsieh Y.-Z; Tseng H.-Y; Chien-Mo J; Liu T.-T; CHIEN-MO LI ; TSUNG-TE LIU Journal of Electronic Testing: Theory and Applications (JETTA)00
62021Chip Performance Prediction Using Machine Learning TechniquesSu M.-Y; Lin W.-C; Kuo Y.-T; Li C.-M; Fang E.J.-W; Hsueh S.S.-Y.; CHIEN-MO LI 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings20
72020Diagnosis technique for Clustered Multiple Transition Delay FaultsYou Y.-S; Liu C.-Y; Wu M.-T; Chen P.-W; Li J.C.-M.; CHIEN-MO LI Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 202030
82020Automatic IR-Drop ECO Using Machine LearningLin H.-Y; Fang Y.-C; Liu S.-T; Chen J.-X; Li C.-M; Fang E.J.-W.; CHIEN-MO LI Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 202050
92020High Efficiency and Low Overkill Testing for Probabilistic CircuitsLee M.-T; Wu C.-H; Liu S.-T; Hsieh C.-Y; Li J.C.-M.; CHIEN-MO LI Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 202010
102020Systematic Hold-time Fault Diagnosis and Failure Debug in Production ChipsLiu C.-Y; Wu M.-T; Li J.C.-M; Bhargava G; Nigh C.; CHIEN-MO LI Proceedings of the Asian Test Symposium10
112020Student engagement in the co-designing and co-teaching a cornerstone eecs design and implementation course at national Taiwan universityLee, J.W.-S.; KUN-YOU LIN ; CHEN HO-LIN ; Chen, J.-P.; SHIH-YUAN CHEN ; CHIEN-MO LI ; Xu, R.-F.; TZI-DAR CHIUEH ; HSIAO-WEN CHUNG ; Chen, N.; CHIEN-MO LI et al. ; KUN-YOU LIN et al. ; SHI-CHUNG CHANG et al. ; SHIH-YUAN CHEN et al. ; TZI-DAR CHIUEH et al. ; HSIAO-WEN CHUNG et al. International Conference on Higher Education Advances00
122019Test methodology for PCHB/PCFB Asynchronous CircuitsShen, T.-Y.; Pai, C.-C.; Chen, T.-C.; Li, J.C.-M.; CHIEN-MO LI ; CHIEN-MO LI Proceedings - International Test Conference10
132019ATPG and test compression for probabilistic circuitsYang, K.-C.; Lee, M.-T.; Wu, C.-H.; Li, J.C.-M.; CHIEN-MO LI 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 201920
142019DR-scan: Dual-rail Asynchronous Scan DfT and ATPGShih-An Hsieh; Ying-Hsu Wang; Ting-Yu Shen; Kuan-Yen Huang; Chia-Cheng Pai Tsai-Chieh Chen; James Chien-Mo Li; CHIEN-MO LI IEEE Transactions on Computer Aided Design22
152018IR drop prediction of ECO-revised circuits using machine learningLin, S.-Y.; Fang, Y.-C.; Li, Y.-C.; Liu, Y.-C.; Yang, T.-S.; Lin, S.-C.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI Proceedings of the IEEE VLSI Test Symposium150
162018Diagnosis and repair of cells (DRC) responsible for power-supply-noise violationsLi, Y.-C.; Lin, S.-Y.; Lin, H.-Y.; Li, J.C.-M.; CHIEN-MO LI 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 201810
172018Parallel order ATPG for test compactionChen, Y.-W.; Ho, Y.-H.; Chang, C.-M.; Yang, K.-C.; Li, M.-T.; Li, J.C.-M.; CHIEN-MO LI 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 201840
182018Machine-learning-based dynamic IR drop prediction for ECOFang, Y.-C.; Lin, H.-Y.; Su, M.-Y.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD300
192018Test pattern compression for probabilistic circuitsChang, C.-M.; Yang, K.-J.; Li, J.C.-M.; CHIEN-MO LI ; CHIEN-MO LI Proceedings of the Asian Test Symposium00
202018Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree constructionWang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI Design Automation Conference50
212018A new method for parameter estimation of high-order polynomial-phase signals.Cao, Runqing; Li, James Chien-Mo; Zuo, Lei; Wang, Zeyu; Lu, Yunlong; CHIEN-MO LI Signal Processing1716
222017Physical-aware diagnosis of multiple interconnect defectsChen, P.-H.; Lee, C.-L.; Chen, J.-Y.; Chen, P.-W.; CHIEN-MO LI ; CHIEN-MO LI ITC-Asia 2017 - International Test Conference in Asia20
232017Robust test pattern generation for hold-time faults in nanometer technologiesHo, Y.-H.; Chen, Y.-W.; Chang, C.-M.; Yang, K.-C.; Li, J.C.-M.; CHIEN-MO LI 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 201710
242017Automatic test pattern generationCheng, K.-T.T.; Wang, L.-C.; Li, H.; Li, J.C.-M.; CHIEN-MO LI Electronic Design Automation for IC System Design, Verification, and Testing00
252017Test Methodology for Dual-rail Asynchronous CircuitsHuang, K.-Y.; Shen, T.-Y.; Li, C.-M.; CHIEN-MO LI Proceedings - Design Automation Conference20
262017PSN-aware Circuit Test Timing Prediction using Machine LearningB. Liu; J. C.M. Li; CHIEN-MO LI IET Computers & Digital Techniques86
272016A multicircuit simulator based on inverse jacobian matrix reuseLee, H.-I.; Han, C.-Y.; Li, J.C.-M.; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
282016Test Pattern Modification for Average IR-Drop ReductionDing, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI IEEE Transactions on Very Large Scale Integration (VLSI) Systems65
292016Power-supply-noise-aware timing analysis and test pattern regenerationHan, C.-Y.; Li, Y.-C.; Kan, H.-T.; Li, J.C.-M.; CHIEN-MO LI IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences00
302015DR Scan: DR-scan: A Test Methodology for Dual-rail Asynchronous CircuitShih-An. Hsieh; Y.-H.Wang; K.Y. Huang; James C.M Li; CHIEN-MO LI Design Automation Conference 
312015TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-internal DefectsA.F. Lin; Kuan-Yu Liao; Kuan-Ying Chiang; James Chien-Mo Li; CHIEN-MO LI IEEE VLSI/DAT 40
322015The Multimedia Piers-Harris Children's Self-Concept Scale 2: Its Psychometric Properties, Equivalence with the Paper-and-Pencil Version, and Respondent PreferencesFlahive, Mon-hsin Wang; Chuang, Ying-Chih; Li, Chien-Mo; CHIEN-MO LI Plos One77
332015Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET CircuitsChiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; CHIEN-MO LI ; CHIEN-MO LI Proceedings of the Asian Test Symposium80
342014GPU-Based Timing-Aware Test Generation for Small Delay DefectsK.Y. Liao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI IEEE European Test Symposium 50
352014Transient IR-drop Analysis for At-speed Testing Using Representative Random WalkM. H. Tsai; W. S. Ding; H. Y. Hsieh; CHIEN-MO LI IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32
362014Physical-aware Systematic Multiple Defect DiagnosisP. J. Chen; C. C. Che; J. C. M. Li; S. F. Kuo; P. Y. Hsueh; C. Y. Kuo; J. N. Lee; CHIEN-MO LI IET Proceedings Computers and Digital Techniques 119
372014Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible ElectronicsY. L. Chen; W. R. Wu; C. N. J. Liu; J. C. M. Li; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2216
382014Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM TestingB.C. Bai; C.A. Chen; J C.M Li; CHIEN-MO LI IEEE International Test Conference 
392014Power-Supply-Noise-Aware Dynamic Timing Analyzer for 3D ICH.Y. Hsieh; J. C.-M. Li; CHIEN-MO LI IEEE 3D IC Test Workshop 
402014GALAXY: A Multi-Circuit Simulator based on Inverse Jacobian Matrix ReuseH.Y. Lee; C.Y. Han; J. C.-M. Li; CHIEN-MO LI IEEE/ACM Design Automation Conference 
412014Divide and Conquer Diagnosis for Multiple DefectsSM Chao; PJ Chen; JCM Li; CHIEN-MO LI IEEE International Test Conference 00
422014Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending EffectsE. H. Ma; W. E. Wei; H. Y. Li; J. C. M. Li; I. C. Cheng; Y. H. Yeh; I-CHUN CHENG ; CHIEN-MO LI IEEE Journal of Display Technology 33
432014GPU-based timing-aware test generation for small delay defects.Liao, Kuan-Yu; Chen, Po-Juei; Lin, Ang-Feng; Li, James Chien-Mo; Hsiao, Michael S.; Wang, Laung-Terng; CHIEN-MO LI 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 201450
442014A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending EffectsWen-En Wei; Hung-Yi Li; Cheng-Yu Han; James Chien-Mo Li; Jian-Jang Huang; I-Chun Cheng; Chien-Nan Liu; Yung-Hui Yeh; I-CHUN CHENG ; JIAN-JANG HUANG ; CHIEN-MO LI Journal of Display Technology52
452014Testing of TSV-induced small delay faults for 3-D integrated circuitsChun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James C.-M. Li; Krishnendu Chakrabarty; YI-CHANG LU ; CHIEN-MO LI IEEE Trans. Very Large Scale Integration (VLSI) Systems1713
462013Compact Test Pattern Selection for Small Delay DefectJ. Y. Chang; K. Y. Liao; S. C. Hsu; J. C. M. Li; J. C. Rau; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1615
472013Test Generation of Path Delay Faults Induced by Defects in Power TSVChi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI IEEE Asian Test Symposium 20
482013Defect Analysis and Fault Modeling for Rnv8T Nonvolatile SRAMBing-Chuan Bai; Chen-An Chen; Yee-Wen Chen; Ming-Hsueh Wu; Kun-Lun Luo; Chun-Lung Hsu; Liang-Chia Cheng; Chien-Mo Li; CHIEN-MO LI IEEE Int’l Test Conf. 
492013Test Pattern Modification for Average IR-drop ReductionWS Ding; HY Hsieh; JCM Li; CHIEN-MO LI IEEE Int’l Test Conf. 
502013Fault Simulation and Test Pattern Selection for Small Delay Defect Using GPUSC Hsu; KY Liao; JCM Li; CHIEN-MO LI VLSI/CAD 
512013Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous TriggeringY. C. Huang; M. H. Tsai; W. S. Ding; J. C. M. Li; M. T. Chang; M. H. Tsai; C. M. Tseng; H. C. Li; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 66
522013Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAMBC Bai; C-L Hsu; MH Wu; CA Chen; YW Chen; KL Luo; LC Cheng; JCM Li; CHIEN-MO LI IEEE Asian Test Symposium 20
532013Testing Leakage Faults of Power TSV in 3D ICChi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI IEEE Int’l workshop on 3D IC 
542013Test generation of path delay faults induced by defects in power TSVShih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; TZONG-LIN WU ; YI-CHANG LU ; CHIEN-MO LI Proceedings of the Asian Test Symposium20
552013Automatic test pattern generation for delay defects using timed characteristic functions.Ho, Shin-Yann; Lin, Shuo-Ren; Yuan, Ko-Lung; Kuo, Chien-Yen; Liao, Kuan-Yu; Jiang, Jie-Hong R.; CHIEN-MO LI ; JIE-HONG JIANG The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 201320
562012A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded CoresG.M. Chiu; J. C. M. Li; CHIEN-MO LI IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6148
572012GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,K. Y. Liao; S. C. Hsu; J. C. M. Li; CHIEN-MO LI Design Automation Conference 120
582012GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPGKY Liao; SC Hsu; JCM Li; CHIEN-MO LI IEEE Int’l Test Conf. 
592012Transient IR-drop Analysis for At-speed Testing Using Representative Random WalkMH Tsai; WS Ting; JCM Li; CHIEN-MO LI VTTW 32
602012Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending EffectsEH Ma; WE Wei; JCM Li; CHIEN-MO LI VLSI/CAD 33
612012Structural Reduction Techniques for Logic-Chain Bridging Fault DiagnosisW.L. Tsai; J. C.M. Li; CHIEN-MO LI IEEE Transactions on Computers 88
622012Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional ICC. J. Shih; C. Y. Hsu; C. Y. Kou; J. C. M. Li; J. C. Rau; K. Chakrabarty; CHIEN-MO LI Active and Passive Electronic Components 70
632012Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling DesignsB. C. Bai; J. C. M. Li; CHIEN-MO LI ITC 
642012Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI IEEE 3D IC Test workshop 
652012Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,M. H. Tsai; W. S. Ting; J. C. M. Li; CHIEN-MO LI ITC 
6620123D IC test scheduling using simulated annealingCY Hsu; CY Kuo; JCM Li; K. Chakrbarty; CHIEN-MO LI IEEE VLSI-DAT 60
672012Systematic Open Via Diagnosis Based on Physical FeaturesP. J. Chen; C. C. Che; J. C. M. Li; K. Y. Tsai; S. F. Kuo; P. Y. Hsueh; Y. Y. Chen; J. N. Lee; CHIEN-MO LI IEEE Silicon Debug and Diagnosis Workshop 
682012Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG ACM Transactions on Design Automation of Electronic Systems (TODAES) 00
692012An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder exampleWang, Y.-S.; Hsieh, M.-H.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN IEEE Transactions on Circuits and Systems I: Regular Papers23
702011A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality ObjectivesLiao, Kuan-Yu; Chang, Chia-Yuan; Li, James Chien-Mo; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1412
712011An Asynchronous Design for Testability and Implementation in Thin-film Transistor TechnologyC. H. Cheng; J. C. M. Li; CHIEN-MO LI Journal of Electronic Testing 88
722011Thermal-aware Test scheduling for 3D ICsCY Hsu; JCM Li; K. Chakrbarty; CHIEN-MO LI IEEE Int’l 3D IC Test Workshop 
732011Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chipsW.C. Wang; J.C.M Li; CHIEN-MO LI IET Computers & Digital Techniques 22
742011Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During ScanR.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI International Test Conference 20
752011Compact test pattern Selection for Small Delay DefectsCY Chang; K.Y, Liao; J.CM Li; CHIEN-MO LI VLSI/CAD 
762011An at-speed self-testable technique for the high speed domino adderWang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Liu, C.-W.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN Proceedings of the Custom Integrated Circuits Conference10
772011Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domainsWu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems41
782011Placement optimization of flexible TFT digital circuitsLiu, W.-H.; Ma, E.-H.; Wei, W.-E.; Li, J.C.-M.; CHIEN-MO LI Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 201110
792011Reliability and Validity Evidence of the Chinese Piers-Harris Children's Self-Concept Scale Scores Among Taiwanese ChildrenFlahive, Mon-hsin Wang; Chuang, Ying-Chih; Li, Chien-Mo; CHIEN-MO LI Journal of Psychoeducational Assessment87
802011Placement optimization of flexible TFT digital circuitsLiu, C.; Ma, E.-H.; Wei, W.-E.; Li, J.; Cheng, I.-C.; Yeh, Y.-H.; I-CHUN CHENG ; CHIEN-MO LI IEEE Design and Test of Computers 44
812010Static timing analysis for flexible TFT circuitsChao-Hsuan Hsu; Liu, C.; En-Hua Ma; Li, J.C.-M.; CHIEN-MO LI Design Automation Conference (DAC) 50
822010CSER: BISER-based concurrent soft-error resilienceLaung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI ; JIUN-LANG HUANG VLSI Test Symposium (VTS) 20
832010DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-inW.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31
842010Method for adjusting clock domain during layout of integrated circuit and associated computer readable mediumJ. Y. Wen; J. C. M. Li; CHIEN-MO LI 
852010Row-LFSR-Column (RLC) Test Response Masking TechniqueWC Wang; JCM Li; CHIEN-MO LI VLSI/CAD 
862010Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> TestingShen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG ; CHIEN-MO LI IEEE/OSA Journal of Display Technology 21
872009Time-space test response compaction and diagnosis based on BCH codesF. M. Wang; W.-C. Wang; J. C-M. Li; CHIEN-MO LI IET Computers & Digital Techniques 00
882009Very-Low-Voltage Testing of Amorphous Silicon TFT CircuitsShiue-Tsung Shen,; Wei-Hsiao Liu,; En-Hua Ma,; J. C.-M. Li,; I-Chun Cheng,; I-CHUN CHENG ; CHIEN-MO LI IEEE Asian Test Symposium 00
892009Bridging Fault Diagnosis to Identify the Layer of Systematic DefectsB. R. Chen; J. C.M. Li; CHIEN-MO LI Asian Test Symposium 30
902009包含未知訊號之測試結果壓縮設計王偉哲 李建模; CHIEN-MO LI 
912009Power Scan: DFT for Power Switches in VLSI DesignsB. C. Bai; CHIEN-MO LI International Test Conference 
922009Test Response Compaction in the Presence of Many UnknownsWei-Che Wang; James C.-M. Lim; Yi-Chih Sung; Amy Rao; Laung-Terng Wang; CHIEN-MO LI VTTW 
932009Electronic Design AutomationJ. C.-M. Li; M. Hsiao; CHIEN-MO LI 
942009Fault Modeling and Testing of Retention Flip-Flops in Low Power DesignsB. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI Asia and South Pacific Design Automation Conference, ASP-DAC 20
952009Transition Fault Diagnosis Using At-speed Test PatternsShang-Feng Chao; Jheng-Yang Ciou; James Chien-Mo Li; CHIEN-MO LI IEEE Int’l Workshop on RTL and High Level Testing 
962009Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits.Shen, Shiue-Tsung; Liu, Wei-Hsiao; Ma, En-Hua; Li, James Chien-Mo; I-CHUN CHENG ; CHIEN-MO LI Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan10
972009Fault Simulation and Test GenerationLi, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI Electronic Design Automation20
982009Power scan: OFT for power switches in VLSI designsBai, B.-C.; Li, C.-M.; Kifli, A.; Tsai, E.; CHIEN-MO LI ; CHIEN-MO LI Proceedings - International Test Conference00
992009BIST design optimization for large-scale embedded memory cores.Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; CHIEN-MO LI ; YAO-WEN CHANG 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 200970
1002008非同步電路可測試設計�G�ҥ� ���ؼ�; CHIEN-MO LI 
1012008可應用於軟性電子的TFT電路設計技術之開發－子計畫六：可應用於軟性電子數位電路測試及容錯技術之開發(2/3)李建模 
1022008Simultaneous capture and shift power reduction test pattern generator for scan testingH.T. Lin; J. C.M. Li; CHIEN-MO LI IET Computers & Digital Techniques 1312
1032008An Asynchronous DFT Technique for TFT MacroelectronicsC. H. Cheng; C.-H. Hsu; J. C.M. Li; CHIEN-MO LI International Symposium on Flexible Electronics and Display (ISFED) 
1042008Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture ClocksShang-Feng Chao; J. C.-M. Li; CHIEN-MO LI VLSI/CAD 
1052008A Dual-rail Asynchronous Scan Chain Design and Its Implementation in TFT TechnologyC. H. Cheng; J. C.M. Li; CHIEN-MO LI VLSI/CAD 
1062008Diagnosis of Logic-chain Bridging FaultsWei-Chih Liu; Wei-Lin Tsai; Hsiu-Ting Lin; James Chien-Mo Li; CHIEN-MO LI IEEE Int’l Workshop on RTL and High Level Testing 00
1072008IEEE 1500 Compatible Secure Test Wrapper For Embedded IP CoresGeng-Ming Chiu; C.-Y. Chiu; R-Y. Wen; James Chien-Mo Li; CHIEN-MO LI International Test Conference 40
1082008Phase Noise Testing of Single Chip TV Tuners,P.-C. Lin; C.-H. Hsu; J. C.-M. Li; C.-M. Chiang; C.-J. Pan,; CHIEN-MO LI IEEE VLSI-DAT 00
1092008Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise,Hsiu-Ting Lin; Jen-Yang Wen; James Li; Ming-Tung Chang; Min-Hsiu Tsai; Sheng-Chih Huang; Chih-Mou Tseng; CHIEN-MO LI Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise 10
1102008Effective and Economic Phase Noise Testing for Single-Chip TV TunersJ. C.-M. Li; P.-C. Lin; P.-C. Chiang; C.-M. Pan; C.W. Tseng; CHIEN-MO LI IEEE Transactions on Instrumentation and Measurement 00
1112008Survey of Scan Chain DiagnosisY. Huang; R Guo; W.T. Cheng; J. C.-M. Li; CHIEN-MO LI IEEE Design & Test of Computers 6150
1122008Diagnosis of Multiple Scan Chain Timing FaultsW.S. Chuang; James C.-M. Li; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 88
1132008On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designsWu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems10
1142008A two-level simultaneous test data and time reduction technique for SOCLiaw, Y.-T.; Bai, B.-C.; Li, J.C.M.; CHIEN-MO LI Journal of Information Science and Engineering1
1152007可應用於軟性電子的TFT電路設計技術之開發－子計畫六：可應用於軟性電子數位電路測試及容錯技術之開發(1/3)李建模 
1162007Design and Chip Implementation of the Segment Weighted Random BIST for Low Power TestingChun-Yi Lee; James C.-M. Li; CHIEN-MO LI Journal of Low Power Electronic 00
1172007適用於建築結構監控之無線感測網路系統－子計畫二：超低功率可容錯及自測基頻通訊積體電路之研製(I)李建模 
1182007奈米IC設計之前瞻電子設計自動化技術－子計畫六：在奈米製程下考量信號完整度之測試與診斷技術　（新制多年期第1年）李建模 
1192007Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and AnalysisJ. C.-M. Li; Hung-Mao Lin; Fang Min Wang; CHIEN-MO LI IEEE Transactions on Computers 73
1202007Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter TechnologiesC.Y. Lee; H.M. Lin; F.M. Wang; J. C. M. Li; CHIEN-MO LI IEEE Asian South Pacific Design Automation Conference (ASP-DAC) 00
1212007Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction TechniqueB.-H. Chen; Wei-Chuang Kao; Bin-Chuan Bai; Shyue-Tsong Shen; James C.-M. Li; CHIEN-MO LI IEEE Asian Test Symposium 00
1222006跳躍式掃描: 低功率可測試設計CHIEN-MO LI ; 邱銘豪; 李建模
1232006Jump Simulation: A Fast and Precise Scan Chain Diagnosis TechniqueY. L Kao; W. S. Chuang; J. C. M Li; CHIEN-MO LI IEEE International Test Conference 330
1242006CRC BIST: A Low Peak Power Self TechniqueBo-Hua Chen; J. C.-M. Li; CHIEN-MO LI VLSI/CAD 
1252006VLSI Test Principles and ArchitecturesWang; Wu; Wen; et. al.; CHIEN-MO LI 
1262006Logic and fault simulationHuang, J.-L.; Li, J.C.-M.; JIUN-LANG HUANG ; CHIEN-MO LI VLSI Test Principles and Architectures00
1272005Diagnosis of Multiple Hold-time and Setup-time Faults in Scan ChainsLi, J. C. M.; CHIEN-MO LI IEEE Transactions on Computers 2829
1282005Diagnosis of Resistive and Stuck-open Defects in Digital CMOS ICLi, J. C.-M.; E. J. McCluskey; CHIEN-MO LI IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4126
1292005掃描鏈中多重時間錯誤之診斷李建模 
1302005Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan ChainsH.M. Lin; J. C. M. Li; CHIEN-MO LI International Test Conference 110
1312005子計畫五：具有自我測試功能之低功率基頻數位收發機電路 設計(1/2)李建模 
1322005Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan ChainsLi, J. C.-M.; CHIEN-MO LI IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3937
1332005Jump Scan: A DFT Technique for Low Power Testing,M.H. Chiu; J. C. M Li; CHIEN-MO LI IEEE VLSI Test Symposium 390
1342005Diagnosis of Timing Faults in Scan Chains Using Single Excitation PatternsLi, J. C.-M.; CHIEN-MO LI IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 55
1352005A Two-level Test Data Compression and Test Time Reduction Technique for SOCYu-Te Liaw; James C.-M. Li; CHIEN-MO LI VLSI/CAD Symposium 
1362005Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power TestingLee, C-Y; Li, C-M; CHIEN-MO LI Asia Solid-State Circuit Conference (ASSCC) 10
1372005Effective and Economic Phase Noise Testing for Single Chip TV TunersP.C. Lin; J. C.-M. Li; Chih-Ming Chiang; Chuo-Jan Pan; CHIEN-MO LI VLSI/CAD Symposium 
1382004單晶片電視調諧器之經濟有效測試方法李建模 
1392004A Design for Testability Technique for Low Power Delay Fault TestingLi, J. C. M.; CHIEN-MO LI IEICE Transactions on Electronics 34
1402004ELF-Murphy Data on Defects and Test SetsE. J. McCluskey; A. Alyamani; J. C. M. Li; C. W. Tseng; E. Volkerink; F. F. Feriani; E. Li; S. Mitra; CHIEN-MO LI IEEE VLSI Test Symposium 440
1412004Diagnosis of Scan Chains with Multiple Timing Faults Using Single Excitation PatternsC. K. Yo; C.M. Li; CHIEN-MO LI VLSI/CAD Symposium 
1422004Design and Implementation of a Low Power Delay Fault Built-in Self Test TechniqueL. W. Ko; C.M. Li; CHIEN-MO LI VLSI/CAD Symposium 
1432004具有內建自我測試功能之5GHz超低功率無線通訊系統之研製─子計畫五：具有自我測試功能之低功率基頻數位收發機電路設計李建模 
1442002Experimental Results for Slow Speed TestingC.W.Tseng; J.C.M. Li; E. J. McCluskey; CHIEN-MO LI IEEE VLSI Test Symposium 70
1452002Diagnosis for Sequence Dependent ChipsLi, J. C.M.; E. J. McCluskey; CHIEN-MO LI IEEE VLSI Test Symposium 430
1462001Diagnosis of Tunneling OpensLi, J. C.M.; E.J. McCluskey; CHIEN-MO LI IEEE VLSI Test Symposium 20
1472001Testing for Resistive and Stuck OpensLi, J. C.M.; Tseng, C.W.; E.J. McCluskey; CHIEN-MO LI International Test Conference 1230
1482001Pseudo Random Testing Theoretical Models vs. Real DataMitra; S.; C.W. Tseng; J. C. M Li; E. J. McCluskey; CHIEN-MO LI IEEE International Workshop on Test Resource Partitioning 
1492000Testing for tunneling opens.Li, Chien-Mo James; McCluskey, Edward J.; CHIEN-MO LI Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 200000
1501998Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.Chang, Jonathan T.-Y.; Tseng, Chao-Wen; Li, Chien-Mo James; Purtell, Mike; McCluskey, Edward J.; CHIEN-MO LI Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 199800
1511998IDDQ data analysis using current signatureLi, J.C.M.; McCluskey, E.J.; CHIEN-MO LI Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998120