第 1 到 42 筆結果,共 42 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2004 | A Design for Testability Technique for Low Power Delay Fault Testing | CHIEN-MO LI | IEICE Transactions on Electronics | |||
2 | 2014 | A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects | Wen-En Wei; Hung-Yi Li; Cheng-Yu Han; James Chien-Mo Li; Jian-Jang Huang; I-Chun Cheng; Chien-Nan Liu; Yung-Hui Yeh; I-CHUN CHENG ; JIAN-JANG HUANG ; CHIEN-MO LI | Journal of Display Technology | 5 | 2 | |
3 | 2011 | A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives | CHIEN-MO LI ; Liao, Kuan-Yu; Chang, Chia-Yuan; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
4 | 2012 | A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores | CHIEN-MO LI ; G.M. Chiu; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 49 | ||
5 | 2011 | An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology | CHIEN-MO LI ; C. H. Cheng; CHIEN-MO LI | Journal of Electronic Testing | 8 | ||
6 | 2012 | An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder example | Wang, Y.-S.; Hsieh, M.-H.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | IEEE Transactions on Circuits and Systems I: Regular Papers | 3 | 3 | |
7 | 2021 | Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits | Chen T.-C; Pai C.-C; Hsieh Y.-Z; Tseng H.-Y; Chien-Mo J; Liu T.-T; CHIEN-MO LI ; TSUNG-TE LIU ; Chiu I.-W | Journal of Electronic Testing: Theory and Applications (JETTA) | 0 | 0 | |
8 | 2007 | Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis | CHIEN-MO LI ; J. C.-M. Li; Hung-Mao Lin; Fang Min Wang; CHIEN-MO LI | IEEE Transactions on Computers | |||
9 | 2013 | Compact Test Pattern Selection for Small Delay Defect | CHIEN-MO LI ; J. Y. Chang; K. Y. Liao; S. C. Hsu; J. C. M. Li; J. C. Rau; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 18 | ||
10 | 2007 | Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing | CHIEN-MO LI ; Chun-Yi Lee; CHIEN-MO LI | Journal of Low Power Electronic | |||
11 | 2010 | DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in | CHIEN-MO LI ; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1 | ||
12 | 2005 | Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains | CHIEN-MO LI | IEEE Transactions on Computers | 31 | ||
13 | 2008 | Diagnosis of Multiple Scan Chain Timing Faults | CHIEN-MO LI ; W.S. Chuang; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | ||
14 | 2005 | Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC | CHIEN-MO LI ; Li, J. C.-M.; E. J. McCluskey; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 26 | ||
15 | 2005 | Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains | CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 38 | ||
16 | 2005 | Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns | CHIEN-MO LI | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 5 | ||
17 | 2019 | DR-scan: Dual-rail Asynchronous Scan DfT and ATPG | Shih-An Hsieh; Ying-Hsu Wang; Ting-Yu Shen; Kuan-Yen Huang; Chia-Cheng Pai Tsai-Chieh Chen; James Chien-Mo Li; CHIEN-MO LI | IEEE Transactions on Computer Aided Design | 3 | 2 | |
18 | 2008 | Effective and Economic Phase Noise Testing for Single-Chip TV Tuners | CHIEN-MO LI ; J. C.-M. Li; P.-C. Lin; P.-C. Chiang; C.-M. Pan; C.W. Tseng; CHIEN-MO LI | IEEE Transactions on Instrumentation and Measurement | 0 | ||
19 | 2014 | Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects | E. H. Ma; W. E. Wei; H. Y. Li; J. C. M. Li; I. C. Cheng; Y. H. Yeh; I-CHUN CHENG ; CHIEN-MO LI | IEEE Journal of Display Technology | 3 | 3 | |
20 | 2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | CHIEN-MO LI ; JIUN-LANG HUANG ; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | 0 | ||
21 | 2016 | A multicircuit simulator based on inverse jacobian matrix reuse | CHIEN-MO LI ; Lee, H.-I.; Han, C.-Y.; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
22 | 2015 | The Multimedia Piers-Harris Children's Self-Concept Scale 2: Its Psychometric Properties, Equivalence with the Paper-and-Pencil Version, and Respondent Preferences | CHIEN-MO LI ; Flahive, Mon-hsin Wang; Chuang, Ying-Chih; CHIEN-MO LI | Plos One | |||
23 | 2018 | A new method for parameter estimation of high-order polynomial-phase signals. | CHIEN-MO LI ; Cao, Runqing; Li, James Chien-Mo; Zuo, Lei; Wang, Zeyu; Lu, Yunlong; CHIEN-MO LI | Signal Processing | |||
24 | 2014 | Physical-aware Systematic Multiple Defect Diagnosis | CHIEN-MO LI ; P. J. Chen; C. C. Che; J. C. M. Li; S. F. Kuo; P. Y. Hsueh; C. Y. Kuo; J. N. Lee; CHIEN-MO LI | IET Proceedings Computers and Digital Techniques | 10 | ||
25 | 2011 | Placement optimization of flexible TFT digital circuits | Liu, C.; Ma, E.-H.; Wei, W.-E.; Li, J.; Cheng, I.-C.; Yeh, Y.-H.; I-CHUN CHENG ; CHIEN-MO LI | IEEE Design and Test of Computers | 4 | 4 | |
26 | 2017 | PSN-aware Circuit Test Timing Prediction using Machine Learning | B. Liu; J. C.M. Li; CHIEN-MO LI | IET Computers & Digital Techniques | 9 | 6 | |
27 | 2011 | Reliability and Validity Evidence of the Chinese Piers-Harris Children's Self-Concept Scale Scores Among Taiwanese Children | CHIEN-MO LI ; Flahive, Mon-hsin Wang; Chuang, Ying-Chih; CHIEN-MO LI | Journal of Psychoeducational Assessment | |||
28 | 2010 | Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> Testing | Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG ; CHIEN-MO LI | IEEE/OSA Journal of Display Technology | 2 | 1 | |
29 | 2011 | Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips | CHIEN-MO LI ; W.C. Wang; CHIEN-MO LI | IET Computers & Digital Techniques | 2 | ||
30 | 2008 | Simultaneous capture and shift power reduction test pattern generator for scan testing | CHIEN-MO LI ; H.T. Lin; CHIEN-MO LI | IET Computers & Digital Techniques | |||
31 | 2014 | Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics | CHIEN-MO LI ; Y. L. Chen; W. R. Wu; C. N. J. Liu; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 16 | ||
32 | 2023 | Small Sampling Overhead Error Mitigation for Quantum Circuits | Hsieh, Cheng Yun; Tsai, Hsin Ying; Lu, Yuan Hsiang; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
33 | 2012 | Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis | CHIEN-MO LI ; W.L. Tsai; CHIEN-MO LI | IEEE Transactions on Computers | 9 | ||
34 | 2008 | Survey of Scan Chain Diagnosis | CHIEN-MO LI ; Y. Huang; R Guo; W.T. Cheng; CHIEN-MO LI | IEEE Design & Test of Computers | |||
35 | 2013 | Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering | CHIEN-MO LI ; Y. C. Huang; M. H. Tsai; W. S. Ding; J. C. M. Li; M. T. Chang; M. H. Tsai; C. M. Tseng; H. C. Li; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
36 | 2016 | Test Pattern Modification for Average IR-Drop Reduction | CHIEN-MO LI ; Ding, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | |||
37 | 2014 | Testing of TSV-induced small delay faults for 3-D integrated circuits | Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James C.-M. Li; Krishnendu Chakrabarty; YI-CHANG LU ; CHIEN-MO LI | IEEE Trans. Very Large Scale Integration (VLSI) Systems | 17 | 13 | |
38 | 2012 | Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC | CHIEN-MO LI ; C. J. Shih; C. Y. Hsu; C. Y. Kou; J. C. M. Li; J. C. Rau; K. Chakrabarty; CHIEN-MO LI | Active and Passive Electronic Components | |||
39 | 2009 | Time-space test response compaction and diagnosis based on BCH codes | CHIEN-MO LI ; F. M. Wang; W.-C. Wang; CHIEN-MO LI | IET Computers & Digital Techniques | 0 | ||
40 | 2014 | Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk | CHIEN-MO LI ; M. H. Tsai; W. S. Ding; H. Y. Hsieh; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 3 | ||
41 | 2008 | A two-level simultaneous test data and time reduction technique for SOC | CHIEN-MO LI ; Liaw, Y.-T.; Bai, B.-C.; CHIEN-MO LI | Journal of Information Science and Engineering | |||
42 | 2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 |