第 1 到 11 筆結果,共 11 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2016 | A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS | Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; SHEN-IUAN LIU ; CHUNG-PING CHEN | IEEE Journal of Solid-State Circuits | 19 | 19 | |
2 | 2015 | A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique | Hung, S.-H.; Kao, W.-H.; Wu, K.-I.; Huang, Y.-W.; Hsieh, M.-H.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | |||
3 | 2015 | A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme | Chien, A.; Hung, S.-H.; Wu, K.-I.; Liu, C.-Y.; Hsieh, M.-H.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | |||
4 | 2013 | A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS | Cheng, W.-S.; Hsieh, M.-H.; Hung, S.-H.; Hung, S.-Y.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | |||
5 | 2013 | A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology | Liu, P.-K.; Hung, S.-Y.; Liu, C.-Y.; Hsieh, M.-H.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | |||
6 | 2012 | An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder example | Wang, Y.-S.; Hsieh, M.-H.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | IEEE Transactions on Circuits and Systems I: Regular Papers | 3 | 3 | |
7 | 2012 | A 6.7MHz-to-1.24GHz 0.0318mm2fast-locking all-digital DLL in 90nm CMOS | Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; CHUNG-PING CHEN | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
8 | 2012 | A 2 -8 GHz multi-phase distributed DLL using phase insertion in 90 nm | Hsieh, M.-H.; Lin, B.-F.; Wang, Y.-S.; Chang, H.-H.; CHUNG-PING CHEN | ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems | |||
9 | 2011 | An at-speed self-testable technique for the high speed domino adder | Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Liu, C.-W.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | Proceedings of the Custom Integrated Circuits Conference | 1 | 0 | |
10 | 2011 | A 12 Gb/s chip-to-chip AC coupled transceiver | Wang, Y.-S.; Hsieh, M.-H.; Wu, Y.-C.; Liu, C.-M.; Chiu, H.-C.; Lin, B.-F.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | |||
11 | 2011 | A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique | Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Wu, Y.-C.; Lin, B.-F.; Chiu, H.-C.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems |