第 1 到 6 筆結果,共 6 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2015 | Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology | Chen, G.-S.; Wu, C.-Y.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 1 | 0 | |
2 | 2015 | 4?25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology | Chiang, P.-C.; Jiang, J.-Y.; Hung, H.-W.; Wu, C.-Y.; Chen, G.-S.; Lee, J.; JRI LEE | IEEE Journal of Solid-State Circuits | 42 | 39 | |
3 | 2014 | 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS | Chiang, P.-C.; Hung, H.-W.; Chu, H.-Y.; Chen, G.-S.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 46 | 0 | |
4 | 2013 | 100Gb/s ethernet chipsets in 65nm CMOS technology | Jiang, J.-Y.; Chiang, P.-C.; Hung, H.-W.; Lin, C.-L.; Yoon, T.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 63 | 0 | |
5 | 2012 | A fully-integrated 40-Gb/s transceiver in 65-nm CMOS technology | Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE | IEEE Journal of Solid-State Circuits | 74 | 64 | |
6 | 2011 | A 40Gb/s TX and RX chip set in 65nm CMOS | Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 20 | 0 |