第 1 到 36 筆結果,共 36 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2011 | Tutorial: "Design of high-speed wireline transceivers". | JRI LEE | IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011 | |||
2 | 2009 | Subharmonically injection-locked PLLS for ultra-low-noise clock generation | Lee, J.; Wang, H.; Chen, W.-T.; Lee, Y.-P.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 11 | 0 | |
3 | 2003 | Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits | Jri Lee; Ken Kundert; Behzad Razavi; JRI LEE | Custom Integrated Circuits Conference | 20 | 0 | |
4 | 2009 | A low-power fully integrated 60ghz transceiver system with OOK modulation and on-board antenna assembly | Lee, J.; Huang, Y.; Chen, Y.; Lu, H.; HSIN-CHIA LU ; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 104 | 0 | |
5 | 2013 | A Fully-Integrated 77GHz phase-array radar system with 1TX/4RX frontend and digital beamforming technique | Huang, S.-J.; Chen, Y.-L.; Chu, H.-Y.; Chen, P.-N.; Chang, H.-Y.; Kuo, C.-Y.; Kao, C.; Lee, J.; JRI LEE | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 9 | ||
6 | 2015 | Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology | Chen, G.-S.; Wu, C.-Y.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 1 | 0 | |
7 | 2010 | A fully integrated 77GHz FMCW radar system in 65nm CMOS | Li, Y.-A.; Hung, M.-H.; Huang, S.-J.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 104 | 0 | |
8 | 1998 | Design of spiral inductors on silicon substrates with a fast simulator | Lee, J.; Kral, A.; Abidi, A.A.; Alexopoulos, N.G.; JRI LEE | European Solid-State Circuits Conference | 30 | 0 | |
9 | 2005 | Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology | Jri Lee; Shanghann Wu; JRI LEE | Symposium on VLSI Circuits | 4 | 0 | |
10 | 2016 | CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS | Chen, L.-Y.; Peng, P.-J.; Kao, C.; Chen, Y.-L.; Lee, J.; JRI LEE | 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings | 2 | 0 | |
11 | 2004 | Analysis and modeling of bang-bang clock and data recovery circuits | Lee, J.; Kundert, K.S.; Razavi, B.; JRI LEE | IEEE Journal of Solid-State Circuits | 199 | 166 | |
12 | 2007 | A 75GHz PLL in 90nmCMOS | JRI LEE | International Solid-State Circuits Conference | |||
13 | 2005 | A 7-band 3-8GHz frequency synthesizer with 1ns band-switching time in 0.18μm CMOS technology | Jri Lee; Da-wei Chiu; JRI LEE | International Solid-State Circuits Conference | 43 | 0 | |
14 | 2008 | A 20Gb/s duobinary transceiver in 90nm CMOS | Jri Lee; M. Chen; H. Wang; JRI LEE | International Solid-State Circuits Conference | 13 | 0 | |
15 | 2007 | A 20Gb/s broadband transmitter with auto-configuration technique | Jri Lee; Huaide Wang; JRI LEE | International Solid-State Circuits Conference | 10 | 0 | |
16 | 2007 | A 20-Gb/s Burst-Mode CDR in 90-nm CMOS | Jri Lee; M. Liu; JRI LEE | International Solid-State Circuits Conference | |||
17 | 2006 | A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology | JRI LEE | International Solid-State Circuits Conference | |||
18 | 2005 | A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-μm CMOS technology | JRI LEE ; Jian-yu Ding; Tuan-yi Cheng | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 13 | 0 | |
19 | 2005 | A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications | SriKanth Gondi; Jri Lee; Behzad Razavi; JRI LEE | International Solid-State Circuits Conference | 63 | 0 | |
20 | 2014 | A 94GHz duobinary keying wireless transceiver in 65nm CMOS | Chen, Y.-L.; Kao, C.; Peng, P.-J.; Lee, J.; JRI LEE | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 6 | 0 | |
21 | 2013 | A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS | Chen, P.-N.; Peng, P.-J.; Kao, C.; Chen, Y.-L.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 26 | 0 | |
22 | 2011 | An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS | Huang, S.-J.; Yeh, Y.-C.; Wang, H.; Chen, P.-N.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 8 | 0 | |
23 | 2014 | A 79-GHz bidirectional pulse radar system with injection-regenerative receiver in 65 nm CMOS | Peng, P.-J.; Kao, C.; Wu, C.-Y.; Lee, J.; JRI LEE | Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium | 3 | 0 | |
24 | 2007 | A 75-GHz PLL in 90-nm CMOS technology | JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
25 | 2014 | 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS | Chiang, P.-C.; Hung, H.-W.; Chu, H.-Y.; Chen, G.-S.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 46 | 0 | |
26 | 2010 | A 60-GHz FSK transceiver with automatically-calibrated demodulator in 90-nm CMOS | Wang, H.; Hung, M.-H.; Yeh, Y.-C.; Lee, J.; JRI LEE | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 23 | 0 | |
27 | 2008 | A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology | Lien, Y.-C.; Lee, J.; JRI LEE | Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | 7 | 0 | |
28 | 2015 | 56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS | Lee, J.; Chiang, P.-C.; Weng, C.-C.; JRI LEE | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 13 | 0 | |
29 | 2017 | A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS | Peng, P.-J.; Li, J.-F.; Chen, L.-Y.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 80 | 0 | |
30 | 2011 | A 40Gb/s TX and RX chip set in 65nm CMOS | Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 20 | 0 | |
31 | 2010 | A 2x25Gb/s deserializer with 2:5 DMUX for 100Gb/s ethernet applications | Wu, K.-C.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 17 | 0 | |
32 | 2010 | A 21-Gb/s 87-mW transceiver with FFE/DFE/analog equalizer in 65-nm CMOS technology | Wang, H.; Lee, J.; JRI LEE | IEEE Journal of Solid-State Circuits | 94 | 84 | |
33 | 2009 | A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition | Lee, J.; Wu, K.-C.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 16 | 0 | |
34 | 2008 | A 20Gb/s Duobinary Transceiver in 90nm CMOS. | Lee, Jri; Chen, Ming-Shuan; Wang, Huaide; JRI LEE | 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008 | 13 | 0 | |
35 | 2007 | A 20Gb/s burst-mode CDR circuit using injection-locking technique | Lee, J.; Mingohung, L.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 30 | 0 | |
36 | 2013 | 100Gb/s ethernet chipsets in 65nm CMOS technology | Jiang, J.-Y.; Chiang, P.-C.; Hung, H.-W.; Lin, C.-L.; Yoon, T.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 63 | 0 |