研究成果

第 1 到 71 筆結果，共 71 筆。

公開日期標題作者來源出版物scopusWOS全文
12023Improved Scalability of Negative Capacitance Junctionless Transistors With Underlap DesignGupta, Manish; VITA PI-HO HU IEEE Transactions on Electron Devices00
22023Stability and Performance Optimization of 6T SRAM Cell at Cryogenic TemperatureFang, Shao Fu; VITA PI-HO HU 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 202310
32023Improved Radiation Hardness for Nanosheet FETs with Partial Bottom Dielectric IsolationZheng, Xun Ting; VITA PI-HO HU 2023 Silicon Nanoelectronics Workshop, SNW 202300
42023Analysis of Monolithic 3D SRAM with Back-End-of-Line-compatible TransistorsLu, Yu Cheng; Lee, Ming; Huang, Zi Yuan; VITA PI-HO HU 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings00
52023Robust Recovery Scheme for MFIS-FeFETs at Optimal Timing with Prolonged Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit DesignWu, C. H.; Liu, J.; Zheng, X. T.; Tseng, Y. M.; Kobayashi, M.; VITA PI-HO HU ; Su, C. J.Technical Digest - International Electron Devices Meeting, IEDM
62022On the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectricSawabe, Yoshiki; Saraya, Takuya; Hiramoto, Toshiro; Su, Chun Jung; VITA PI-HO HU ; Kobayashi, MasaharuApplied Physics Letters55
72022Variation-Tolerant Recall Operation for Nonvolatile SRAM Integrated with Ferroelectric CapacitorLi, Ai Fang; Huang, Ruei Yu; VITA PI-HO HU 6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 202210
82022Energy-and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible TransistorsLee, Ming; Huang, Zi Yuan; Fan, Shao Fu; Lu, Yu Cheng; VITA PI-HO HU Technical Digest - International Electron Devices Meeting, IEDM00
92022Efficient Erase Operation by GIDL Current for 3D Structure FeFETs with Gate Stack Engineering and Compact Long-Term Retention ModelMo F; Xiang J; Mei X; Sawabe Y; Saraya T; Hiramoto T; Su C.-J; VITA PI-HO HU ; Kobayashi M.IEEE Journal of the Electron Devices Society33
1020222D Materials-Based Static Random-Access MemoryLiu C.-J; Wan Y; Li L.-J; Lin C.-P; Hou T.-H; Huang Z.-Y; VITA PI-HO HU Advanced Materials1014
112022Sensitivity Analysis of Ferroelectric Junctionless Transistors for Non-volatile Memory ApplicationsGupta M; VITA PI-HO HU 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 202210
122021Identical Pulse Programming Based Ultra-Thin 5 nm HfZrO2Ferroelectric Field Effect Transistors with High Conductance Ratio and Linearity Potentiation Learning TrajectoryLiao C.-Y; VITA PI-HO HU et al. ECS Journal of Solid State Science and Technology22
132021Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-term FeFET Retention ModelMo F; Xiang J; Mei X; Sawabe Y; Saraya T; Hiramoto T; Su C.-J; VITA PI-HO HU ; Kobayashi M.Digest of Technical Papers - Symposium on VLSI Technology4
142021Static Noise Margin Analysis for Cryo-CMOS SRAM CellLiu C.-J.; VITA PI-HO HU 2021 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 202130
152021Improved switching time in negative capacitance junctionless transistorsGupta M; VITA PI-HO HU VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings00
162021Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless TransistorsGupta M; Hu V.P.-H.; VITA PI-HO HU ECS Journal of Solid State Science and Technology22
172021High-Density and High-Speed 4T FinFET SRAM for Cryogenic ComputingVITA PI-HO HU ; Liu C.-J; Chiang H.-L; Wang J.-F; Cheng C.-C; Chen T.-C; Chang M.-F.Technical Digest - International Electron Devices Meeting, IEDM60
182021Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance ApplicationsGupta M; VITA PI-HO HU IEEE Transactions on Electron Devices22
192021Monolithic 3D SRAM cell with stacked two-dimensional materials based FETs at 2nm nodeSu C.-W; Yu C.-C; Liu C.-J; Weng C.-Y.; VITA PI-HO HU Proceedings - IEEE International Symposium on Circuits and Systems20
202020Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power ApplicationsM. Gupta; V. P.-H. Hu; VITA PI-HO HU ; M. Gupta; V. P.-H. Hu; 胡璧合 IEEE Electron Device Letters2121
212020Optimization of Negative-Capacitance Vertical-Tunnel FET(NCVT-FET)H.-H. Lin; Y.-K. Lin; C. Hu; VITA PI-HO HU IEEE Transactions on Electron Devices4943
222020Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS<inf>2</inf>FETs for SoC ScalingSu, C.-W.; Lee, Y.-W.; Ho, T.-Y.; Cheng, C.-C.; Chen, T.-C.; Hung, T.Y.-T.; Li, J.-F.; Chen, Y.-G.; Li, L.-J.; VITA PI-HO HU IEEE Transactions on Electron Devices910
232020Subthreshold Behavior of Ferroelectric Junctionless TransistorHu V.P.-H.; VITA PI-HO HU 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 202000
2420203D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafersSu, Chunjung; Huang, Minkun; Lee, K. S.; VITA PI-HO HU ; Huang, Y. F.; Zheng, B. C.; Yao, C. H.; Lin, Neichih; Kao, Kuo-Hsing Hsing; Hong, Tzu Chieh; Sung, Pojung; Wu, Chienting; Yu, Tungyuan; Lin, Kun–Lin; Tseng, Y. C.; Lin, C. L.; Lee, Yaojen; Chao, Tiensheng; JIUN-YUN LI ; Wu, Wenfa; Shieh, Jiaming; Wang, Yeong-Her; Yeh, WenkuanTechnical Digest - International Electron Devices Meeting, IEDM50
252019Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETsP.-C. Chiu; Y.-C. Lu; VITA PI-HO HU IEEE Journal of the Electron Devices Society1920
262019Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power ApplicationsGupta M; Hu V.P.-H.; VITA PI-HO HU 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 201900
272019Evaluation of analog circuit performance for ferroelectric SOI MOSFETs considering interface trap charges and gate length variationsLu Y.-C; Hu V.P.-H.; VITA PI-HO HU 2019 Silicon Nanoelectronics Workshop, SNW 201970
282019Improved read stability and writability of negative capacitance FinFET SRAM cell for subthreshold operationZheng Z.-A; Hu V.P.-H.; VITA PI-HO HU Proceedings - IEEE International Symposium on Circuits and Systems70
292019Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic ApplicationsLin H.-H; Zheng Z.-A; Lin Z.-T; Lu Y.-C; Ho L.-Y; Lee Y.-W; Su C.-W; Su C.-J.; VITA PI-HO HU Digest of Technical Papers - Symposium on VLSI Technology180
302019Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FETLin H.-H; Hu V.P.-H.; VITA PI-HO HU Proceedings - International Symposium on Quality Electronic Design, ISQED40
312019Reduced RTN amplitude and single trap induced variation for ferroelectric FinFET by substrate doping optimizationLin Z.-T; Hu V.P.-H.; VITA PI-HO HU 2019 Silicon Nanoelectronics Workshop, SNW 201910
322018Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETsP.-C. Chiu; VITA PI-HO HU Japanese Journal of Applied Physics12
332018Analysis of heterojunction GaAs1-xSbx/In1-yGayAs tunnel FETs considering line tunnelingWang C.-T; Hu V.P.-H.; VITA PI-HO HU Proceedings - 2018 7th International Symposium on Next-Generation Electronics, ISNE 201800
342018Optimization of III-V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppressionC.-T. Wang; VITA PI-HO HU Japanese Journal of Applied Physics1210
352018Device Designs of III-V Tunnel FETs for Performance Enhancements through Line TunnelingWang C.-T; Hu V.P.-H.; VITA PI-HO HU 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings40
362018Negative capacitance enables FinFET and FDSOI scaling to 2 nm nodeHu V.P.-H; Chiu P.-C; Sachid A.B; Hu C.; VITA PI-HO HU Technical Digest - International Electron Devices Meeting, IEDM170
372018Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function VariationChiu P.-C; Hu V.P.-H.; VITA PI-HO HU 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings40
382017Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense AmplifierV. P.-H. Hu; VITA PI-HO HU ; V. P.-H. Hu; 胡璧合 IEEE Journal of the Electron Devices Society87
392017Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETsChiu P.-C; Hu V.P.-H.; VITA PI-HO HU 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings50
402016Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM ApplicationsC.-H. Yu; M.-L. Fan; K.-C. Yu; Pin Su; C.-T. Chuang; VITA PI-HO HU IEEE Transactions on Electron Devices1617
412016Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETsVITA PI-HO HU ; Su P; Chuang C.-T.Proceedings - IEEE International Symposium on Circuits and Systems20
422015Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FETC.-W. Hsu; M.-L. Fan; V. P.-H. Hu; Pin Su; VITA PI-HO HU ; C.-W. Hsu; M.-L. Fan; V. P.-H. Hu; Pin Su; 胡璧合 IEEE Journal of the Electron Devices Society200
432015Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-AssistM.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU IEEE Transactions on Electron Devices139
442015Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cellsVITA PI-HO HU ; Fan M.-L; Su P; Chuang C.-T.Proceedings - IEEE International Symposium on Circuits and Systems20
452015Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA CircuitsY.-N. Chen; C.-J. Chen; M.-L. Fan; Pin Su; C.-T. Chuang; VITA PI-HO HU Journal of Low Power Electronics and Applications90
462015Stability analysis for UTB GeOI 6T SRAM cells considering NBTI and PBTIVITA PI-HO HU ; Fan M.-L; Su P; Chuang C.-T.International Symposium on VLSI Technology, Systems, and Applications, Proceedings00
472015Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FETM.-L. Fan; V. P.-H. Hu; Y.-N. Chen; C.-W. Hsu; Pin Su; C.-T. Chuang; VITA PI-HO HU ; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; C.-W. Hsu; Pin Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Electron Devices2420
482014Evaluation of Stabilit, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist CircuitsY.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合 IEEE Journal on Emerging and Selected Topics in Circuits and Systems4638
492014Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuitsM.-L. Fan; S.-Y. Yang; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU Microelectronics Reliability2322
502014Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET DevicesY.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Circuits and Systems I: Regular Papers139
512014Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer CouplingM.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU ; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Electron Devices86
522014Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cellsVITA PI-HO HU ; Fan M.-L; Su P; Chuang C.-T.Proceedings - IEEE International Symposium on Circuits and Systems00
532013Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFETV. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU ; V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Electron Devices2220
542013Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FETM.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU ; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Electron Devices5548
552013Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM CellsV. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU ; V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Electron Devices76
562013Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold OperationV. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU ; V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Nanotechnology75
572013Design and Analysis of Robust Tunneling FET SRAMY.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; 胡璧合 IEEE Transactions on Electron Devices3630
582012Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETsC.-H. Yu; Y.-S. Wu; P. Su; VITA PI-HO HU IEEE Transactions on Nanotechnology119
592012Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor StackingM.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU IEEE Electron Device Letters1410
602012Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic CircuitsM.-L. Fan; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU IEEE Transactions on Electron Devices3934
612012Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMsC.-Y. Hsieh; M.-L. Fan; VITA PI-HO HU IEEE Transactions on Very Large Scale Integration (VLSI) Systems4029
622012Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM ApplicationsM.-L. Fan; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU IEEE Transactions on Circuits and Systems II: Express Briefs1712
632012Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETsC.-H. Yu; Y.-S. Wu; P. Su; VITA PI-HO HU IEEE Transactions on Electron Devices66
642011Investigation of Electrostatic Integrity for Ultrathin-Body Germanium-On-Nothing MOSFETY.-S. Wu; P. Su; VITA PI-HO HU IEEE Transactions on Nanotechnology119
652011Impact of quantum confinement on short-channel effects for ultrathin-body germanium-on-insulator MOSFETsWu Y.-S; Hsieh H.-Y; VITA PI-HO HU ; Su P.IEEE Electron Device Letters2014
662011FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate DielectricsM.-L. Fan; C.-Y. Hsieh; P. Su; C.-T. Chuang; VITA PI-HO HU IEEE Transactions on Electron Devices3322
672011Comparison of 4T and 6T FinFET SRAM cells for subthreshold operation considering variability-A model-based approachFan M.-L; Wu Y.-S; VITA PI-HO HU ; Hsieh C.-Y; Su P; Chuang C.-T.IEEE Transactions on Electron Devices3422
682011Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature SensitivityM.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU IEEE Journal on Emerging and Selected Topics in Circuits and Systems44
692010Investigation of cell stability and write ability of finfet subthreshold SRAM using analytical SNM modelFan M.-L; Wu Y.-S; VITA PI-HO HU ; Su P; Chuang C.-T.IEEE Transactions on Electron Devices3320
702009Investigation of static noise margin of ultra-thin-body SOI SRAM cells in subthreshold region using analytical solution of poisson's equationVITA PI-HO HU ; Wu Y.-S; Fan M.-L; Su P; Chuang C.-T.International Symposium on VLSI Technology, Systems, and Applications, Proceedings00
712009Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells—An Assessment Based on Analytical Solutions of Poisson's EquationY.-S. Wu; M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU IEEE Transactions on Electron Devices75