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.National Taiwan University / 國立臺灣大學
Project / 研究計畫
iChip兆級智慧矽晶片之研究:演算法,架構,與實現技術-子計畫二:適用於智慧應用之兆級可重組化多核心串流處理器架構之研究
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iChip兆級智慧矽晶片之研究:演算法,架構,與實現技術-子計畫二:適用於智慧應用之兆級可重組化多核心串流處理器架構之研究
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Primary Data
Project title
iChip兆級智慧矽晶片之研究:演算法,架構,與實現技術-子計畫二:適用於智慧應用之兆級可重組化多核心串流處理器架構之研究
Internal ID
97-2221-E-002-243-MY3
Principal Investigator
SHAO-YI CHIEN
Start Date
August 1, 2008
End Date
July 31, 2009
Partner Organizations
National Science and Technology Council