A High Dynamic Range, Low Gain Error Programmable Gain Amplifier for Powerline Communication Systems
Date Issued
2012
Date
2012
Author(s)
Chan, Kai-Hsiang
Abstract
Todays, Internet communication such as Ethernet and wireless are inseparable with our daily life. Besides, Power-Line Communication (PLC) will be a new scheme for household and office. The wire cost benefits of PLC outweigh Ethernet due to PLC used original power line as transmission wire. Moreover, PLC system is more stable than wireless internet and is able to transmit signals without interference from walls. Therefore, PLC system will take an important role of internet communication in the future development.
Two low power and wide gain range programmable gain amplifiers (PGAs) were designed for HomePlug AV standards. The coarse and fine tune skills are used in PGA design to reduce programmable gain stages, wide gain range and power consumption. For circuit operation purpose, the current compensation technique is used in PGA design to stabilize gain step. Furthermore, the linear-in-decibel gain characteristics are implemented by pseudo-exponential function with transconductor units.
The first PGA integrated chip was fabricated in TSMC CMOS 0.18μm process. According to measurement results, the performance shows 1dBm P1dB, 10.39dBm IIP3, -24.26dB voltage gain at lowest gain mode, and 98.67dB gain range with 1.57dB resolution while consuming 1.99mW at 1.8-V supply voltage. The core area is 0.225 x 0.13mm2.
The second PGA chip was fabricated in TSMC CMOS 90nm process, integrated into PLC system as an analog front-end (AFE) circuit. The PLC transceiver includes a programmable gain amplifier (PGA), an analog-to-digital converter (ADC), a line driver, and a digital-to-analog converter (DAC). To achieve higher data rate, the bandwidth and gain range were designed to be 373.79MHz, 41.42dB (-20.921~20.499dB) with 0.32dB resolution. In addition, the signal through PGA and ADC has 7.3bits ENOB and 46dB SNDR. The whole chip (PLC) area is 2.63 x 2.52mm2, and PGA area is 0.15 x 0.11 mm2.
Subjects
PGA
PLC
Low Gain Error
High Dynamic Range
MTPR
Reconfigurable
Type
thesis
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