2.8 to 67.2mW low-power and power-aware H.264 encoder for mobile applications
Journal
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages
222-223
Date Issued
2007
Author(s)
Abstract
A 2.8 to 67.2mW H.264 encoder is implemented on a 12.8mm2 die with 0.18μm CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock.
Event(s)
2007 Symposium on VLSI Circuits, VLSIC
Other Subjects
Algorithms; Data processing; Reusability; Data reuse schemes; Gated clock; Mobile applications; System hierarchy; CMOS integrated circuits
Type
conference paper