An algorithmic error-resilient scheme for robust LDPC decoding
Journal
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Date Issued
2015
Author(s)
Abstract
To fit into multiple communication standards, flexible Low-Density Parity-Check (LDPC) decoding is desirable to be implemented in a chip multiprocessor (CMP) system. However, reliability issues, such as soft errors and timing errors, are severer in future advanced CMP systems when CMOS technology scale. Therefore, enhancing error resilience for a CMP system becomes an important design issue. In this paper, we propose a design methodology to achieve a robust LDPC decoding based on algorithmic error-resilient method. We firstly analyze the performance degradation caused by the soft errors which occur in the computing units (check node units and bit node units), and then explore the inherent error-tolerant characteristic of LDPC decoding algorithm. In our proposed method, we exploit some characteristic distribution or behavior in the operations of the LDPC decoding algorithm to validate the computing results. The experimental results show that the proposed algorithmic error resilience can approach the error-free decoder while facing high injected soft-error rate of 10 ?3 in computing units, but with only 6.07% computational overhead. To the best of our knowledge, this is the first discussion about the LDPC decoding algorithm in terms of soft errors in computing units.
Type
conference paper