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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Design of a Low-Power, Delay Line Using Gated-Driver Tree
Details
Design of a Low-Power, Delay Line Using Gated-Driver Tree
Journal
15th VLSI Design/CAD Symposium
Date Issued
2004-08
Author(s)
P. C. Hsieh
J. S. Jhuang
TZI-DAR CHIUEH
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/310914
Type
conference paper