Efficient Booth Multiplier and Reed-Solomon Codec Architecture Design and Implementation
Date Issued
2007
Date
2007
Author(s)
Song, Min-An
DOI
zh-TW
Abstract
No matter in what field the circuit is applied, we can always innovate or improve the high efficiency architecture by using the optimal algorithm. We have also implemented the optimal algorithm on the most popular circuits currently used. In this paper we presented some of our research results and innovation, which actually improve the efficiency architecture and algorithm. We also proposed new structures of generally low error, low area, fixed-width multiplier and the design of a decoder for large scale disk array system.
Due to the fast development of digital signal processing and wireless/wired communication techniques, the demand for high speed, low area and low power becomes more and more urgent. The development of a good algorithm and architecture will largely reduce the design cost in the levels of logic, circuit and layout. The new or improved version of architecture and algorithm in this paper will illuminate the efficiency for some point while sacrificing some efficiency of the other. We did find some low error, low area fixed-width multiplier. We proposed two efficient architectures and algorithms, the Binary-Thresholding Method and Binary-Condition Method, which are new generally low error and low area fixed-width multiplier. Due to the lower truncation error this new multiplier has better waveforms for consonants and vowels. The improved fixed-width multiplier has been implemented as a single chip with a TSMC 0.35μm process, and operates under 3.3V and 66MHz.
Along with the development of internet and various multimedia data base, a large scale storage system (such as a large scale disk array system) has become more and more important. In addition to providing a high speed interface for user access, it also has to provide a very stable data storage environment to prevent the loss of valuable data due to a variety of possible causes. We have applied methods with hardware or software to deal with every possible threatening situations (such as heat noise, machine malfunction, unfavorable preserving environment or transmission passages, etc.) to assure the storage or transmission of data reliable and correct. Among the various fault-tolerant techniques the error correction code is the most important one. We have developed the optimal algorithm and architecture for error correction code and have designed to cope with various environment in order to overcome data loss in various situations. We have used Altera Stratix FPGA device (EP1S10F484C5) to realize the RS codec.
Subjects
固定寬度乘法器
容錯技術
李德所羅門編解碼器
fixed-width multiplier
Binary-Thresholding
RS codec
Type
thesis
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