Variation-Resilient Design Techniques for Energy-Constrained Systems.
Journal
2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019
Pages
228-231
Date Issued
2019
Author(s)
Wu, Bing-Chen
Abstract
Process, voltage, and temperature (PVT) variations substantially increase the variability of digital CMOS logics and reduce the operation robustness, especially for energy-constrained systems with aggressive voltage scaling. This paper reviews several variation-resilient design techniques for addressing PVT variations to improve the energy efficiency of digital CMOS VLSI circuits. The scope includes static and adaptive design techniques for design-time and run-time optimization, respectively. In addition, an emerging adaptive design strategy combining the fully integrated voltage regulator for system-level optimization is also introduced. © 2019 IEEE.
Subjects
adaptive design.; and temperature (PVT) variations; Fully integrated voltage regulator; process; variation-resilient techniques; voltage
SDGs
Other Subjects
CMOS integrated circuits; Electric potential; Energy efficiency; Processing; Systems analysis; Voltage regulators; Voltage scaling; Adaptive design techniques; Adaptive designs; Aggressive voltage scaling; and temperature (PVT) variations; Energy constrained systems; Fully integrated; System level optimization; variation-resilient techniques; Integrated circuit design
Type
conference paper