具有內建自我測試功能之5GHz 超低功率無線通訊系統之研製— 子計畫六：超低功率無線通訊晶片之系統設計與整合(1/2)
Date Issued
2005
Date
2005
Author(s)
DOI
932220E002013
Abstract
In this year, we propose the implementation of two
chips. (1) A reconfigurable decoder IC for Irregular
LDPC codes. (2) A mixed signal Rake receiver. In
(1), we started from surveying the decoding
algorithms of LDPC, and designed a hardware
architecture to implement the decoding algorithm
and meet the reconfigurable requirement.
Afterwards, we did the system simulation and
compared the performance with the Viterbi decoding
algorithm. Now we are doing the step of hardware
implementation including the RTL coding of the
digital circuit and the full-custom design of memory
blocks. In (2), we proposed an analog Rake receiver.
It can lessen the receiver power consumption as
compared to digital Rake receiver and maintain the
advantage of the overall system by incorporating
the analog correlator to reduce the power
consumption of analog to digital converter.
Subjects
Irregular Low-density Parity Check
Code
Code
Reconfigurable Decoder IC
Analog to
Digital Converter
Digital Converter
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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932220E002013.pdf
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Format
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(MD5):8b08610b05ef9f54bdbcaa6be3b41f3a