XNOR-Based Double-Edge-Triggered Flip-Flop for Two-Phase Pipelines
Resource
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 2, FEBRUARY 2006
Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS
Journal Volume
VOL. 53
Journal Issue
NO. 2
Pages
-
Date Issued
2006-02
Date
2006-02
Author(s)
Shu, Ying-Haw
Tenqchen, Shing
Sun, Ming-Chang
Feng, Wu-Shiung
DOI
246246/200611150121895
Abstract
The conventional approach of double-edge-triggered
flip-flops (DET-FFs) is to have two similar edge-triggered latches.
And the achieved faster speed is at the cost of double chip area
and complex logic structure. By contrast, the XNOR-based approaches
is difficult to reach the speed demand due to the delay
of the XNOR-based clock generator. This paper proposes a new
designed DET-FF based on an alternative XNOR gate. By utilizing
the sensitivity to the driving capacity of the previous stage, we use
this simplified XNOR gate as a pulse-generator. A modified transparent
latch following the pulse-generator acts as an XNOR-based
DET-FF, which accomplishes the almost same speed and less
power dissipation as compared with two conventional DET-FFs
under HSPICE simulation. We also implemented the XNOR-based
DET-FF in a two-phase-pipeline system, and the HSPICE simulation
in the TSMC 0.25 um CMOS process shows our proposed
DET-FF is much faster than those two conventional DET-FFs.
Subjects
Double-edge triggered (DET)
pipeline
two
phase
phase
XNOR
Publisher
Taipei:National Taiwan University Dept Elect Engn
Type
journal article
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