A PSRR-enhanced low-dropout regulator
Journal
IET Electronics Letters
Journal Volume
47
Journal Issue
1
Pages
17-18
Date Issued
2011-01
Author(s)
Wei-Jen Huang
Abstract
A power supply rejection ratio (PSRR) enhancement technique for the low-dropout regulator (LDR) is presented. This proposed LDR with a bandgap reference has been fabricated in a 0.35 ?m CMOS process, and its active chip area is 0.1978 mm2. From experimental results, the proposed LDR provides a stable output voltage without the output capacitor and achieves over a PSRR of ?76 dB at 100 kHz for the output current within 0�V150 mA. In addition, the output integrated noise is 21.45 ?Vrms within a frequency between 22 Hz and 80 kHz.
SDGs
Type
journal article