Rapid Prototyping and VLSI Architecture of the Feed-forward Error Correction Subsystems for Digital Video Transmission (Ⅲ)
Date Issued
2001-07-31
Date
2001-07-31
Author(s)
DOI
892218E002109
Abstract
Recent rapid progress in VLSI
technology has led to an emerging theme
－ “System-on-a-chip.” The complexity
of new design paradigm is much higher
than conventional IC designs. Hence, it
calls for rapid prototyping and design
reuse of major IP modules so as to
alleviate the designer's effort and to speed
up the design process.
In this project, we will develop a
knowledge-based CAD tool to assist the
IC designers with the Feed-forward Error
Correction (FEC) subsystems in our group
project － “Digital Video Transmission
System.” The CAD tool can take the
system specification such as m, n, t of
Reed Solomon (RS) codec. Then the code
generator will follow the design
methodology to automatically generate
synthesizable Verilog codes for ASIC
and/or FPGA implementations. Thus, the
system IC designer can focus on
system-level design issues without going
through tedious designs of the FEC
modules. We first go through the complete
ASIC design flow to explore the design
techniques in RS codec and Interleaver /
De-interleaver. The design experience will
be formulated to form the complete design
methodology of the FEC modules at the
register-transfer level (RTL). Then we
incorporate the knowledge into our CAD
tool design flow. We consider this research
work as our first step towards the
emerging area－CAD for DSP. Also, it
provides a good example for rapid
prototyping of a reconfigurable IP design
in communication system.
Subjects
Intellectual property (IP)
Computer-aided design (CAD)
Digital
signal processor (DSP)
signal processor (DSP)
Reed-Solomon
codec
codec
Interleaver/De-interleaver
Design
automation
automation
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
File(s)![Thumbnail Image]()
Loading...
Name
892218E002109.pdf
Size
322.19 KB
Format
Adobe PDF
Checksum
(MD5):a6fc456059820bd52833a1e6499d9a1a