High-Speed Circuit Designs for Transmitters in Broadband Data Links
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
41
Journal Issue
5
Pages
1004 - 1015
Date Issued
2006-05
Author(s)
Abstract
Various high-speed techniques including internal peaking, differentially stacked inductor, and dual-loop PLL for wireline communications are proposed,analyzed, and verified by means of three independent circuits. A multiplexer incorporates multiple peaking techniques and gate control switching to achieve an operation speed of 20 Gb/s while consuming 22 mW from a 1.8-V supply. A voltage-controlled oscillator employing differentially stacked inductor accomplishes a phase noise of -90dBc/Hzat 1-MHz offset with a minimum power of 1 mW. A clock multiplication unit utilizes dual-loop architecture as well as a third-order loop filter, arriving at an output jitter of 0.2 ps, rms (0.87 ps, rms de-embedding 0.84 ps, rms from the instruments) and 4.5 ps, pp while consuming 40 mW from a 1.8-V supply.
SDGs
Type
journal article