Design and VLSI implementation of real-time weighted median filters
Resource
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Journal
IEEE Asia-Pacific Conference on Circuits and Systems, 1994. APCCAS '94
Pages
-
Date Issued
1994-12
Date
1994-12
Author(s)
DOI
N/A
Abstract
In this paper, a novel design method and VLSI implementation of weighted median filters is presented. The weight parameters are incremented to minimize the mean square error of the input signal and desired signal when the sub-set of the image data is applied. The suboptimal(optimal) weight set is achieved after 71 training cycles for 5*5 window size under the MSE criteria. A two-level adder tree architecture with pipelined latches is proposed to find the weighted median output with versatile definition of weight. It requires only K iterations to find output, where K means the resolution of the input signal samples. The task interleaved processing is also adopted to improve the throughput. The final chip layout with pipelined latches for 5*5 window size is also given in this paper. This high-speed VLSI implementation of weighted median filter will meet the real-time application requirements.
Type
journal article
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