High-Level Design Intent Extraction for Intelligent Verification
Date Issued
2007
Date
2007
Author(s)
Chang, Chi-Wen
DOI
en-US
Abstract
High-level design intents such as finite state machine (FSM) and counter are commonly used in modern VLSI design. We can use them to guide the exploration of the design space and thus improve the verification efficiency. However, previous works on high-level intent extraction can only identify very limited constructs such as explicit FSM in restricted coding style. In this work, we propose a novel technique which can extract all the explicit, implicit FSMs and the counter. We also prove with several theorems that our algorithms are very robust and not limited to the coding styles and the HDL synthesizable subset. The experimental results on several real designs demonstrate that our program is superior over existing commercial tools.
Subjects
有限狀態機
暫存器轉移層
FSM RTL
Design Intent
Extraction
Type
thesis
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