A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS
Journal
International Solid-State Circuits Conference (ISSCC) 2007
Pages
48-49
Date Issued
2007-02
Author(s)
Abstract
A 33.6-to-33.8 Gb/s burst-mode CDR circuit is realized in 90nm CMOS technology. The LC gated VCO, the phase selector the input matching circuit, and the wideband data buffer are discussed. With 2n-1 PRBS input, the measured rms jitter for the recovered data is 1.15ps at 33.72Gb/s. This CDR can tolerate 31 consecutive identical bits with a locking time of 0.2ns (<7b interval). It consumes 73mW from a 1.2V supply excluding the buffers.
SDGs
Type
conference paper