A Low Power 200MS/s, 10bit Pipelined Analog to Digital Converter
Date Issued
2011
Date
2011
Author(s)
Hsieh, Yi-Chun
Abstract
In high speed, medium-high resolution analog-to-digital converter (ADC), the pipelined architecture is the most common used. To reduce the power consumption, the capacitor-sharing technique is used in [1], [2], [3], [4]. Conventional capacitor-sharing technique employed the discharge phase to cancel the charge on feedback capacitor. However, the discharge phase occupied the amplification phase, and power consumption is raised. In additional, conventional capacitor-sharing technique is also only applied in first stage. In proposed work, the discharge phase is removed, and capacitor-sharing technique is applied to first and second stage; hence the power consumption is further reduced.
A 10-bit pipelined ADC with 1.2V, 200MS/s, in 90nm technology is proposed. In 200MS/s with 1.99MHz input, the signal to noise and distortion ratio is 53.14dB. In 200MS/s with 99.9MHz input, the SNDR is 50.25dB. Integral Nonlinearity and differential nonlinearity are +1.59/-1.91 LSB and +0.70/-0.75 LSB respectively. The power consumption is 45.4mW at 1.2V power supply. The ADC occupies an active area of 0.53 mm2.
Subjects
pipelined ADC
low-power
high-speed
Type
thesis
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