Analog Placement with Symmetry and Regularity Considerations
Date Issued
2011
Date
2011
Author(s)
Chou, Pang-Yen
Abstract
Symmetry constraints and regular structures are two major considerations for expert analog layout designers. Symmetry constraints are specified by designers to place matched modules symmetrically with respect to some common axes to reduce unwanted electrical effects. Regular structures are commonly followed by experienced analog layout designers to enhance routability and suppress parasitics induced by extra bends of wires and via cost. In this thesis, we propose a heterogeneous B*-tree representation to consider symmetry and regularity simultaneously. Corresponding moves and a new regularity cost modeling for the representation are also presented. Experimental results show that our approach can efficiently generate regularly structured placement satisfying all symmetry constraints. For example, our placer achieves a 18X runtime speedup, 28% smaller area, and 68% shorter wire length than the previous work, based on placement results, and 60% fewer overflows, 39% fewer vias, and 86% shorter routed wirelength, based on global routing results.
Subjects
physical design
analog placement
symmetry constraint
regular structure
hierarchical B*-tree
Type
thesis
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