Algorithms and Hardware Architectures for Variable Block Size Motion Estimation
Date Issued
2009
Date
2009
Author(s)
Weng, Chih-Hung
Abstract
Multimedia has become more and more important in embedded systems. It isell-known that the motion estimation plays an essential role in video coding. Its also the key elements that achieve video compression by exploiting temporaledundancy of video data because the di erence between two successive framesre usually very small, especially for high frame rates.he latest coding standard H.264 has adopted lots of new features. For in-tance, in order to adaptively choose the proper block size for frame macroblock,.264 has used variable block size motion estimation which can signi cantly im-rove the coding performance compared to previous techniques. However, theomputational complexity of H.264 has also increased drastically. Among all theechniques in the encoder, motion estimation is exactly the most time-consumingunction especially when it is implemented in a software approach.n this thesis, we combine software and hardware optimizations for variablelock size motion estimation. At the software level, we propose a new algorithmhat can e ciently select a suitable block size by grouping the motion vectors. Athe hardware level, we propose a pipelined and parallel architecture to enhancehe performance. Our architecture is implemented on an FPGA platform. Itperates at a maximum clock frequency of 311 MHz with gate count 65k. Theesults show that under a frequency of 248MHz, our architecture allows the pro-essing of 1920x1080 at 30fps with full search motion estimation in a 16x16 searchange. This proposed architecture provides a better hardware e ciency in termsf throughput and gate count than previous works.
Subjects
Motion Estimation
VBSME
Hardware Accelerator
Type
thesis
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