Dual-band CDR using a half-rate linear phase detector
Journal
IEEE International SOC Conference, SOCC 2009
Pages
51-54
Date Issued
2009
Author(s)
Abstract
This paper describes a dual-band clock and data recovery circuit using a new half-rate linear phase detector. With the proposed sampling scheme, the phase detector produces UP/DN signals with equal pulsewidth and thus eliminates the demand of current scaling in the charge pump. The test chip fabricated by CMOS 0.18 �gm 1P6M process can operate at 2.7 and 1.62 Gbps which satisfies the DisplayPort standard. It can recover the NRZ data of a (2 7 -1) PRBS with a bit error rate less than 10 ?12 . The chip core occupies an area of 0.36 mm 2 . The power consumption is 50 mW at 2.7 Gbps with a 1.8 V supply voltage.
SDGs
Type
conference paper