Power-Aware Rendering Engine Design for Small-Panel Display System
Date Issued
2006
Date
2006
Author(s)
Chao, Chih-Hao
DOI
en-US
Abstract
System level power consumption is essential design consideration for current mobile devices. There are more and more designer emphasizes the importance of realtime computer graphic in small-panel display system. Consider the high complexity of realtime computer graphic algorithms, commercial graphic processing units adopt highly parallelized architecture and operate at high frequency. The power consumption of these GPUs is huge and therefore not suitable for mobile devices. Consequently, to design low power and high efficiency rendering engine for small-panel mobile devices is necessary to extend the operating time.
In this thesis, we improve the existing rendering algorithm and propose a power-aware system architecture including three key modules: dynamic task dispatcher, dynamic task scheduler, and 2-stage precision-aware processor array. The proposed algorithm and architecture efficiently raise the power efficiency. We use Verilog HDL to design our system at RT-level, and follow the standard cell-based design flow to complete the design and verification. The synthesized area using TSMC 0.18μm process is 1.6mm2, and the maximum operating frequency is 100MHz. The power efficiency of our design is 2Mpixels/s/mW.
Subjects
繪圖引擎
功率感知
顯示系統
Power-Aware
Rendering
Rendering Engine
Scan converting algorithm
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-95-R93943026-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):cd41de1e4859c07d9c54c8851148c85f