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  4. Negative capacitance enables FinFET and FDSOI scaling to 2 nm node
 
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Negative capacitance enables FinFET and FDSOI scaling to 2 nm node

Journal
Technical Digest - International Electron Devices Meeting, IEDM
Date Issued
2018
Author(s)
Hu V.P.-H
Chiu P.-C
Sachid A.B
Hu C.
VITA PI-HO HU  
DOI
10.1109/IEDM.2017.8268443
URI
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85045215162&doi=10.1109%2fIEDM.2017.8268443&partnerID=40&md5=7854b7a24232c8ff1df7557918b5a24c
https://scholars.lib.ntu.edu.tw/handle/123456789/581194
Abstract
The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wfin) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/μm and 10%?29% higher Ion compared with 2nm FinFET(97μA/μm Ioff) and FDSOI(46μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI. ? 2017 IEEE.
Subjects
Capacitance; Nanotechnology; Back-gate bias; Channel thickness; Fin widths; Negative capacitance; Scaling limits; TCAD simulation; Technology nodes; FinFET
Type
conference paper

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