Delta-Sigma ADC for Biomedical Electronic Applications
Date Issued
2016
Date
2016
Author(s)
Chang, Po-Jung
Abstract
As the IC industry getting flourish, wearable devices become gradually important in daily life. Among them, biomedical electronic is one of the famous topics. Because of the extremely small of the biomedical signal, to obtain the accurate consequences, a system that combines a high resolution analog front-end circuit with sensors is required. Nevertheless, dealing with biomedical signals always has problem with baseline drifting which limits the gain of the front-end amplifier. Thus, the resolution demands of analog to digital converter (ADC) become higher. Although successive approximate register (SAR) ADC can operate in mediate speed and has the advantage of low power consumption, its resolution is restricted by the size of the capacitor. When encountering the requirement of resolution that exceeds 12-bit, the design complexity and power dissipation of SAR ADC will increase dramatically. Most of biomedical signals are under 1 kHz, which exactly fit the characteristic of delta-sigma ADC for its low operation frequency. With the help of noise shaping, the quantization noise at low frequency can be reduced. Simultaneously, sampling frequency is several times higher than the signal frequency can depress the in-band noise. Through above two features, delta-sigma ADC can achieve high resolution easily. In this thesis, the design method of implementation of delta-sigma ADC for biomedical applications is proposed. It includes the plan of the whole system specifications, front-end MATLAB simulation process, derivation of circuit principles, and considerations of real circuit implementation. With this flow, two delta-sigma ADC were taped out, and the results correctly met previous simulations. To meet the trend of biomedical sensor requirement, the chips were fabricated by the process of UMC 0.18 um. Both of the designs employ CIFF-B 3rd order architecture, which contains two feedback paths and a feed-forward path to reduce power dissipation. The power of the first chip totally consumes 384.21 uW and achieves effect number of bits of 12.83 bits. The second chip is relatively outstanding. Its design not only change the structure of the integrator to reduce unnecessary power dissipation but also adds a resonance feedback loop. With the notch characteristic on noise shaping, the performance of the circuits is enhanced. The total power of the chip is lower to 260 uW and ENOB reaches 14.7892 bits.
Subjects
Delta-sigma modulator
noise shaping
oversampling
low power
continuous-time
Type
thesis
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