Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Layout techniques for on-chip interconnect inductance reduction
Details
Layout techniques for on-chip interconnect inductance reduction
Journal
Asia and South Pacific Design Automation Conference, ASP-DAC
Pages
269-273
Date Issued
2004
Author(s)
Tu, S.-W.
Jou, J.-Y.
YAO-WEN CHANG
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-2442531922&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/309297
Type
conference paper