Design of a 1-V 20-GHz Phase-Locked Loop in 0.18-um CMOS
Date Issued
2009
Date
2009
Author(s)
Fang, Yu-Hsien
Abstract
In this work, a 20-GHz PLL with a 1-V supply is designed, where a pair of cross-coupled capacitors, Cf, is proposed and added to the LC-VCO. The two capacitors are inserted between the output and the gate of cross-coupled pair in the LC-VCO, and therefore lower the equivalent capacitance at output while looking into the series connection of Cf and the gate capacitance of cross-coupled pair. The LC-VCO uses this configuration, and therefore makes the output oscillation frequency raised by 1.0 GHz approximately. Besides, the LC-VCO employing a differential, geometrically symmetrical with high Q inductor and lowering the transconductance of cross-coupled pair accomplishes a phase noise of －106-dBc/Hz at 1-MHz offset with a minimum power of 1-mW.requency divider plays an essential role in a PLL system. In divider chain, the injection-locked frequency dividers are employed in the first and the second stage dividers. By selecting an adequate load inductor, the first and the second injection-locked frequency dividers operate at desired center frequency accordingly. Whereas, in order to ensure the frequency dividers can functionally work, a parameter, locking range, therefore becomes the most important design target especially for high-speed frequency dividers applications. This thesis provides a rapid and roughly accurate estimation of divider locking range, so as to increase design efficiency in injection-locked frequency dividers.n the divider chain of this work, current-mode logic based frequency dividers are adopted in four-stage cascaded-dividers after two-cascaded-stage injection-locked frequency dividers, arriving at a wide-locking-range characteristic. According to the post-layout simulations of the third to the seventh stages frequency dividers, they achieve a 1.2 to 7.3-GHz locking range wide. This result demonstrates the third to seventh stage frequency dividers can correctly operate under possible PVT variations.he transistor-level and 2.5-D EM co-simulation results of the PLL reveal that the PLL is locked at 20.6 GHz, and it achieves a magnitude of －46.6-dBc reference spurs with a 1-MHz loop bandwidth and a 160.93-MHz reference frequency, while consuming 18.5 mW from a 1-V supply.
Subjects
Phase-locked loop (PLL)
voltage-controlled oscillator (VCO)
Miller divider
frequency divider
reference spurs
low-voltage
Type
thesis
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